#include <s5pc210.h>

typedef unsigned char	bool;
#include "cmu.h"

#define SYSC_DMUX	1	//TRUE
#define SYSC_NMUX	0	//false
#define SYSC_TEST	1	//TRUE
#define SYSC_NOTEST	0	//false

#define TRUE		1
#define FALSE		0

#define Inp32(addr) 		(*(volatile u32 *)(addr))
#define Outp32(addr, data) 	(*(volatile u32 *)(addr) = (data))

#define GetBits(uAddr, uBaseBit, uMaskValue) \
		((Inp32(uAddr)>>(uBaseBit))&(uMaskValue))

#define SetBits(uAddr, uBaseBit, uMaskValue, uSetValue) \
		Outp32(uAddr, (Inp32(uAddr) & ~((uMaskValue)<<(uBaseBit))) | (((uMaskValue)&(uSetValue))<<(uBaseBit)))

static enum CLK_CON_REG
{
	rCLK_SRC_LEFTBUS		=SYSC_CMU_TOP_BASE+0x4200,
	rCLK_MUX_STAT_LEFTBUS		=SYSC_CMU_TOP_BASE+0x4400,
	rCLK_DIV_LEFTBUS		=SYSC_CMU_TOP_BASE+0x4500,
	rCLK_DIV_STAT_LEFTBUS		=SYSC_CMU_TOP_BASE+0x4600,
	rCLK_GATE_IP_LEFTBUS		=SYSC_CMU_TOP_BASE+0x4800,
	rCLKOUT_CMU_LEFTBUS 		=SYSC_CMU_TOP_BASE+0x4A00,
	rCLKOUT_CMU_LEFTBUS_DIV_STAT	=SYSC_CMU_TOP_BASE+0x4A04,
	rCMU_LEFTBUS_SPARE0 		=SYSC_CMU_TOP_BASE+0x4B00,
	rCMU_LEFTBUS_SPARE1 		=SYSC_CMU_TOP_BASE+0x4B04,
	rCMU_LEFTBUS_SPARE2 		=SYSC_CMU_TOP_BASE+0x4B08,
	rCMU_LEFTBUS_SPARE3 		=SYSC_CMU_TOP_BASE+0x4B0C,
	rCMU_LEFTBUS_SPARE4 		=SYSC_CMU_TOP_BASE+0x4B10,
	rCLK_SRC_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8200,
	rCLK_MUX_STAT_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8400,
	rCLK_DIV_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8500,
	rCLK_DIV_STAT_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8600,
	rCLK_GATE_IP_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8800,
	rCLKOUT_CMU_RIGHTBUS		=SYSC_CMU_TOP_BASE+0x8A00,
	rCLKOUT_CMU_RIGHTBUS_DIV_STAT	=SYSC_CMU_TOP_BASE+0x8A04,
	rCMU_RIGHTBUS_SPARE0		=SYSC_CMU_TOP_BASE+0x8B00,
	rCMU_RIGHTBUS_SPARE1		=SYSC_CMU_TOP_BASE+0x8B04,
	rCMU_RIGHTBUS_SPARE2		=SYSC_CMU_TOP_BASE+0x8B08,
	rCMU_RIGHTBUS_SPARE3		=SYSC_CMU_TOP_BASE+0x8B0C,
	rCMU_RIGHTBUS_SPARE4		=SYSC_CMU_TOP_BASE+0x8B10,
	rEPLL_LOCK			=SYSC_CMU_TOP_BASE+0xC010,
	rVPLL_LOCK			=SYSC_CMU_TOP_BASE+0xC020,
	rEPLL_CON0			=SYSC_CMU_TOP_BASE+0xC110,
	rEPLL_CON1			=SYSC_CMU_TOP_BASE+0xC114,
	rVPLL_CON0			=SYSC_CMU_TOP_BASE+0xC120,
	rVPLL_CON1			=SYSC_CMU_TOP_BASE+0xC124,
	rCLK_SRC_TOP0			=SYSC_CMU_TOP_BASE+0xC210,
	rCLK_SRC_TOP1			=SYSC_CMU_TOP_BASE+0xC214,
	rCLK_SRC_CAM			=SYSC_CMU_TOP_BASE+0xC220,
	rCLK_SRC_TV 			=SYSC_CMU_TOP_BASE+0xC224,
	rCLK_SRC_MFC			=SYSC_CMU_TOP_BASE+0xC228,
	rCLK_SRC_G3D			=SYSC_CMU_TOP_BASE+0xC22C,
	rCLK_SRC_IMAGE			=SYSC_CMU_TOP_BASE+0xC230,
	rCLK_SRC_LCD0			=SYSC_CMU_TOP_BASE+0xC234,
	rCLK_SRC_LCD1			=SYSC_CMU_TOP_BASE+0xC238,
	rCLK_SRC_MAUDIO 		=SYSC_CMU_TOP_BASE+0xC23C,
	rCLK_SRC_FSYS			=SYSC_CMU_TOP_BASE+0xC240,
	rCLK_SRC_PERIL0 		=SYSC_CMU_TOP_BASE+0xC250,
	rCLK_SRC_PERIL1 		=SYSC_CMU_TOP_BASE+0xC254,
	rCLK_SRC_MASK_TOP		=SYSC_CMU_TOP_BASE+0xC310,
	rCLK_SRC_MASK_CAM		=SYSC_CMU_TOP_BASE+0xC320,
	rCLK_SRC_MASK_TV		=SYSC_CMU_TOP_BASE+0xC324,
	rCLK_SRC_MASK_LCD0		=SYSC_CMU_TOP_BASE+0xC334,
	rCLK_SRC_MASK_LCD1		=SYSC_CMU_TOP_BASE+0xC338,
	rCLK_SRC_MASK_MAUDIO		=SYSC_CMU_TOP_BASE+0xC33C,
	rCLK_SRC_MASK_FSYS		=SYSC_CMU_TOP_BASE+0xC340,
	rCLK_SRC_MASK_PERIL0		=SYSC_CMU_TOP_BASE+0xC350,
	rCLK_SRC_MASK_PERIL1		=SYSC_CMU_TOP_BASE+0xC354,
	rCLK_MUX_STAT_TOP		=SYSC_CMU_TOP_BASE+0xC410,
	rCLK_MUX_STAT_MFC		=SYSC_CMU_TOP_BASE+0xC428,
	rCLK_MUX_STAT_G3D		=SYSC_CMU_TOP_BASE+0xC42C,
	rCLK_MUX_STAT_IMAGE 		=SYSC_CMU_TOP_BASE+0xC430,
	rCLK_DIV_TOP			=SYSC_CMU_TOP_BASE+0xC510,
	rCLK_DIV_CAM			=SYSC_CMU_TOP_BASE+0xC520,
	rCLK_DIV_TV 			=SYSC_CMU_TOP_BASE+0xC524,
	rCLK_DIV_MFC			=SYSC_CMU_TOP_BASE+0xC528,
	rCLK_DIV_G3D			=SYSC_CMU_TOP_BASE+0xC52C,
	rCLK_DIV_IMAGE			=SYSC_CMU_TOP_BASE+0xC530,
	rCLK_DIV_LCD0			=SYSC_CMU_TOP_BASE+0xC534,
	rCLK_DIV_LCD1			=SYSC_CMU_TOP_BASE+0xC538,
	rCLK_DIV_MAUDIO 		=SYSC_CMU_TOP_BASE+0xC53C,
	rCLK_DIV_FSYS0			=SYSC_CMU_TOP_BASE+0xC540,
	rCLK_DIV_FSYS1			=SYSC_CMU_TOP_BASE+0xC544,
	rCLK_DIV_FSYS2			=SYSC_CMU_TOP_BASE+0xC548,
	rCLK_DIV_FSYS3			=SYSC_CMU_TOP_BASE+0xC54C,
	rCLK_DIV_PERIL0 		=SYSC_CMU_TOP_BASE+0xC550,
	rCLK_DIV_PERIL1 		=SYSC_CMU_TOP_BASE+0xC554,
	rCLK_DIV_PERIL2 		=SYSC_CMU_TOP_BASE+0xC558,
	rCLK_DIV_PERIL3 		=SYSC_CMU_TOP_BASE+0xC55C,
	rCLK_DIV_PERIL4 		=SYSC_CMU_TOP_BASE+0xC560,
	rCLK_DIV_PERIL5 		=SYSC_CMU_TOP_BASE+0xC564,
	rCLKDIV2_RATIO			=SYSC_CMU_TOP_BASE+0xC580,
	rCLK_DIV_STAT_TOP		=SYSC_CMU_TOP_BASE+0xC610,
	rCLK_DIV_STAT_CAM		=SYSC_CMU_TOP_BASE+0xC620,
	rCLK_DIV_STAT_TV		=SYSC_CMU_TOP_BASE+0xC624,
	rCLK_DIV_STAT_MFC		=SYSC_CMU_TOP_BASE+0xC628,
	rCLK_DIV_STAT_G3D		=SYSC_CMU_TOP_BASE+0xC62C,
	rCLK_DIV_STAT_IMAGE		=SYSC_CMU_TOP_BASE+0xC630,
	rCLK_DIV_STAT_LCD0		=SYSC_CMU_TOP_BASE+0xC634,
	rCLK_DIV_STAT_LCD1		=SYSC_CMU_TOP_BASE+0xC638,
	rCLK_DIV_STAT_MAUDIO		=SYSC_CMU_TOP_BASE+0xC63C,
	rCLK_DIV_STAT_FSYS0 		=SYSC_CMU_TOP_BASE+0xC640,
	rCLK_DIV_STAT_FSYS1 		=SYSC_CMU_TOP_BASE+0xC644,
	rCLK_DIV_STAT_FSYS2 		=SYSC_CMU_TOP_BASE+0xC648,
	rCLK_DIV_STAT_FSYS3 		=SYSC_CMU_TOP_BASE+0xC64C,
	rCLK_DIV_STAT_PERIL0		=SYSC_CMU_TOP_BASE+0xC650,
	rCLK_DIV_STAT_PERIL1		=SYSC_CMU_TOP_BASE+0xC654,
	rCLK_DIV_STAT_PERIL2		=SYSC_CMU_TOP_BASE+0xC658,
	rCLK_DIV_STAT_PERIL3		=SYSC_CMU_TOP_BASE+0xC65C,
	rCLK_DIV_STAT_PERIL4		=SYSC_CMU_TOP_BASE+0xC660,
	rCLK_DIV_STAT_PERIL5		=SYSC_CMU_TOP_BASE+0xC664,
	rCLKDIV2_STAT			=SYSC_CMU_TOP_BASE+0xC680,
	rCLK_GATE_IP_CAM		=SYSC_CMU_TOP_BASE+0xC920,
	rCLK_GATE_IP_TV 		=SYSC_CMU_TOP_BASE+0xC924,
	rCLK_GATE_IP_MFC		=SYSC_CMU_TOP_BASE+0xC928,
	rCLK_GATE_IP_G3D		=SYSC_CMU_TOP_BASE+0xC92C,
	rCLK_GATE_IP_IMAGE		=SYSC_CMU_TOP_BASE+0xC930,
	rCLK_GATE_IP_LCD0		=SYSC_CMU_TOP_BASE+0xC934,
	rCLK_GATE_IP_LCD1		=SYSC_CMU_TOP_BASE+0xC938,
	rCLK_GATE_IP_FSYS		=SYSC_CMU_TOP_BASE+0xC940,
	rCLK_GATE_IP_GPS		=SYSC_CMU_TOP_BASE+0xC94C,
	rCLK_GATE_IP_PERIL		=SYSC_CMU_TOP_BASE+0xC950,
	rCLK_GATE_IP_PERIR		=SYSC_CMU_TOP_BASE+0xC960,
	rCLK_GATE_BLOCK 		=SYSC_CMU_TOP_BASE+0xC970,
	rCLKOUT_CMU_TOP 		=SYSC_CMU_TOP_BASE+0xCA00,
	rCLKOUT_CMU_TOP_DIV_STAT	=SYSC_CMU_TOP_BASE+0xCA04,
	rCMU_TOP_SPARE0 		=SYSC_CMU_TOP_BASE+0xE000,
	rCMU_TOP_SPARE1 		=SYSC_CMU_TOP_BASE+0xE004,
	rCMU_TOP_SPARE2 		=SYSC_CMU_TOP_BASE+0xE008,
	rCMU_TOP_SPARE3 		=SYSC_CMU_TOP_BASE+0xE00C,
	rCMU_TOP_SPARE4 		=SYSC_CMU_TOP_BASE+0xE010,
	rCLK_SRC_CORE			=SYSC_CMU_CORE_BASE+0x0200,
	rCLK_SRC_MASK_CORE		=SYSC_CMU_CORE_BASE+0x0300,
	rCLK_MUX_STAT_CORE		=SYSC_CMU_CORE_BASE+0x0400,
	rCLK_DIV_CORE0			=SYSC_CMU_CORE_BASE+0x0500,
	rCLK_DIV_CORE1			=SYSC_CMU_CORE_BASE+0x0504,
	rCLK_DIV_STAT_CORE0 		=SYSC_CMU_CORE_BASE+0x0600,
	rCLK_DIV_STAT_CORE1 		=SYSC_CMU_CORE_BASE+0x0604,
	rCLK_GATE_IP_CORE		=SYSC_CMU_CORE_BASE+0x0900,
	rCLKOUT_CMU_CORE		=SYSC_CMU_CORE_BASE+0x0A00,
	rCLKOUT_CMU_CORE_DIV_STAT	=SYSC_CMU_CORE_BASE+0x0A04,
	rDCGIDX_MAP0			=SYSC_CMU_CORE_BASE+0x1000,
	rDCGIDX_MAP1			=SYSC_CMU_CORE_BASE+0x1004,
	rDCGIDX_MAP2			=SYSC_CMU_CORE_BASE+0x1008,
	rDCGPERF_MAP0			=SYSC_CMU_CORE_BASE+0x1020,
	rDCGPERF_MAP1			=SYSC_CMU_CORE_BASE+0x1024,
	rDVCIDX_MAP			=SYSC_CMU_CORE_BASE+0x1040,
	rFREQ_CPU			=SYSC_CMU_CORE_BASE+0x1060,
	rFREQ_DPM			=SYSC_CMU_CORE_BASE+0x1064,
	rDVSEMCLK_EN			=SYSC_CMU_CORE_BASE+0x1080,
	rMAXPERF			=SYSC_CMU_CORE_BASE+0x1084,
	rCMU_CORE_SPARE0		=SYSC_CMU_CORE_BASE+0x2000,
	rCMU_CORE_SPARE1		=SYSC_CMU_CORE_BASE+0x2004,
	rCMU_CORE_SPARE2		=SYSC_CMU_CORE_BASE+0x2008,
	rCMU_CORE_SPARE3		=SYSC_CMU_CORE_BASE+0x200C,
	rCMU_CORE_SPARE4		=SYSC_CMU_CORE_BASE+0x2010,
	rAPLL_LOCK			=SYSC_CMU_CORE_BASE+0x4000,
	rMPLL_LOCK			=SYSC_CMU_CORE_BASE+0x4008,
	rAPLL_CON0			=SYSC_CMU_CORE_BASE+0x4100,
	rAPLL_CON1			=SYSC_CMU_CORE_BASE+0x4104,
	rMPLL_CON0			=SYSC_CMU_CORE_BASE+0x4108,
	rMPLL_CON1			=SYSC_CMU_CORE_BASE+0x410C,
	rCLK_SRC_CPU			=SYSC_CMU_CORE_BASE+0x4200,
	rCLK_MUX_STAT_CPU		=SYSC_CMU_CORE_BASE+0x4400,
	rCLK_DIV_CPU0			=SYSC_CMU_CORE_BASE+0x4500,
	rCLK_DIV_CPU1			=SYSC_CMU_CORE_BASE+0x4504,
	rCLK_DIV_STAT_CPU0		=SYSC_CMU_CORE_BASE+0x4600,
	rCLK_DIV_STAT_CPU1		=SYSC_CMU_CORE_BASE+0x4604,
	rCLKOUT_CMU_CPU 		=SYSC_CMU_CORE_BASE+0x4A00,
	rCLKOUT_CMU_CPU_DIV_STAT	=SYSC_CMU_CORE_BASE+0x4A04,
	rARMCLK_STOPCTRL		=SYSC_CMU_CORE_BASE+0x5000,
	rATCLK_STOPCTRL 		=SYSC_CMU_CORE_BASE+0x5004,
	rARM_MCS_CTRL			=SYSC_CMU_CORE_BASE+0x5008,
	rARM_MCS_STATUS 		=SYSC_CMU_CORE_BASE+0x500C,
	rPARITYFAIL_STATUS		=SYSC_CMU_CORE_BASE+0x5010,
	rPARITYFAIL_CLEAR		=SYSC_CMU_CORE_BASE+0x5014,
	rAPLL_CON0_L8			=SYSC_CMU_CORE_BASE+0x5100,
	rAPLL_CON0_L7			=SYSC_CMU_CORE_BASE+0x5104,
	rAPLL_CON0_L6			=SYSC_CMU_CORE_BASE+0x5108,
	rAPLL_CON0_L5			=SYSC_CMU_CORE_BASE+0x510C,
	rAPLL_CON0_L4			=SYSC_CMU_CORE_BASE+0x5110,
	rAPLL_CON0_L3			=SYSC_CMU_CORE_BASE+0x5114,
	rAPLL_CON0_L2			=SYSC_CMU_CORE_BASE+0x5118,
	rAPLL_CON0_L1			=SYSC_CMU_CORE_BASE+0x511C,
	rIEM_CONTROL			=SYSC_CMU_CORE_BASE+0x5120,
	rAPLL_CON1_L8			=SYSC_CMU_CORE_BASE+0x5200,
	rAPLL_CON1_L7			=SYSC_CMU_CORE_BASE+0x5204,
	rAPLL_CON1_L6			=SYSC_CMU_CORE_BASE+0x5208,
	rAPLL_CON1_L5			=SYSC_CMU_CORE_BASE+0x520C,
	rAPLL_CON1_L4			=SYSC_CMU_CORE_BASE+0x5210,
	rAPLL_CON1_L3			=SYSC_CMU_CORE_BASE+0x5214,
	rAPLL_CON1_L2			=SYSC_CMU_CORE_BASE+0x5218,
	rAPLL_CON1_L1			=SYSC_CMU_CORE_BASE+0x521C,
	rCLKDIV_IEM_L8			=SYSC_CMU_CORE_BASE+0x5300,
	rCLKDIV_IEM_L7			=SYSC_CMU_CORE_BASE+0x5304,
	rCLKDIV_IEM_L6			=SYSC_CMU_CORE_BASE+0x5308,
	rCLKDIV_IEM_L5			=SYSC_CMU_CORE_BASE+0x530C,
	rCLKDIV_IEM_L4			=SYSC_CMU_CORE_BASE+0x5310,
	rCLKDIV_IEM_L3			=SYSC_CMU_CORE_BASE+0x5314,
	rCLKDIV_IEM_L2			=SYSC_CMU_CORE_BASE+0x5318,
	rCLKDIV_IEM_L1			=SYSC_CMU_CORE_BASE+0x531C,
	rCMU_CPU_SPARE0 		=SYSC_CMU_CORE_BASE+0x6000,
	rCMU_CPU_SPARE1 		=SYSC_CMU_CORE_BASE+0x6004,
	rCMU_CPU_SPARE2 		=SYSC_CMU_CORE_BASE+0x6008,
	rCMU_CPU_SPARE3 		=SYSC_CMU_CORE_BASE+0x600C,
	rCMU_CPU_SPARE4 		=SYSC_CMU_CORE_BASE+0x6010
};

static enum CLK_CON_HIDDEN_REG
{
	rCLK_GATE_BUS_LEFTBUS	=SYSC_CMU_TOP_BASE+0x4700,
	rCLK_GATE_BUS_RIGHTBUS	=SYSC_CMU_TOP_BASE+0x8700,
	rCLK_GATE_BUS_CAM	=SYSC_CMU_TOP_BASE+0xC720,
	rCLK_GATE_BUS_TV	=SYSC_CMU_TOP_BASE+0xC724,
	rCLK_GATE_BUS_MFC	=SYSC_CMU_TOP_BASE+0xC728,
	rCLK_GATE_BUS_G3D	=SYSC_CMU_TOP_BASE+0xC72C,
	rCLK_GATE_BUS_IMAGE 	=SYSC_CMU_TOP_BASE+0xC730,
	rCLK_GATE_BUS_LCD0	=SYSC_CMU_TOP_BASE+0xC734,
	rCLK_GATE_BUS_LCD1	=SYSC_CMU_TOP_BASE+0xC738,
	rCLK_GATE_BUS_FSYS	=SYSC_CMU_TOP_BASE+0xC740,
	rCLK_GATE_BUS_GPS	=SYSC_CMU_TOP_BASE+0xC74C,
	rCLK_GATE_BUS_PERIL 	=SYSC_CMU_TOP_BASE+0xC750,
	rCLK_GATE_BUS_PERIR 	=SYSC_CMU_TOP_BASE+0xC760,
	rCLK_GATE_SCLK_CAM	=SYSC_CMU_TOP_BASE+0xC820,
	rCLK_GATE_SCLK_TV	=SYSC_CMU_TOP_BASE+0xC824,
	rCLK_GATE_SCLK_MFC	=SYSC_CMU_TOP_BASE+0xC828,
	rCLK_GATE_SCLK_G3D	=SYSC_CMU_TOP_BASE+0xC82C,
	rCLK_GATE_SCLK_IMAGE	=SYSC_CMU_TOP_BASE+0xC830,
	rCLK_GATE_SCLK_LCD0 	=SYSC_CMU_TOP_BASE+0xC834,
	rCLK_GATE_SCLK_LCD1 	=SYSC_CMU_TOP_BASE+0xC838,
	rCLK_GATE_SCLK_MAUDIO	=SYSC_CMU_TOP_BASE+0xC83C,
	rCLK_GATE_SCLK_FSYS 	=SYSC_CMU_TOP_BASE+0xC840,
	rCLK_GATE_SCLK_PERIL	=SYSC_CMU_TOP_BASE+0xC850,
	rCLK_GATE_BUS_CORE0 	=SYSC_CMU_CORE_BASE+0x0700,
	rCLK_GATE_BUS_CORE1 	=SYSC_CMU_CORE_BASE+0x0704,
	rCLK_GATE_SCLK_CORE 	=SYSC_CMU_CORE_BASE+0x0800,
	rCLK_GATE_SCLK_CPU	=SYSC_CMU_CORE_BASE+0x4800
};

typedef struct tag_MUX_SEL
{	
	char strName[30];
	u32 uSetAddr;
	u32 uMonAddr;
	u32 uOffset;
	u32 uMaskBit;
	bool bIsDmux;
	bool bUse;
} oMUX_SEL;

static oMUX_SEL aoMuxSel[]=
{
	{ "MUX_GDL",  rCLK_SRC_LEFTBUS ,  rCLK_MUX_STAT_LEFTBUS ,  0,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_GDR",  rCLK_SRC_RIGHTBUS ,  rCLK_MUX_STAT_RIGHTBUS ,  0,  1,  SYSC_DMUX,  SYSC_TEST },

	{ "MUX_ONENAND",  rCLK_SRC_TOP0 ,  rCLK_MUX_STAT_TOP ,	28,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_ACLK_133",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  24,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_ACLK_160",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  20,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_ACLK_100",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  16,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_ACLK_200",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  12,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_VPLL",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  8,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_EPLL",  rCLK_SRC_TOP0 ,	rCLK_MUX_STAT_TOP ,  4,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_VPLLSRC",  rCLK_SRC_TOP1 ,  rCLK_SRC_MASK_TOP ,	0,	1,	SYSC_NMUX,	SYSC_TEST },
	{ "MUX_CSIS1",	rCLK_SRC_CAM ,	rCLK_SRC_MASK_CAM ,  28,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_CSIS0",	rCLK_SRC_CAM ,	rCLK_SRC_MASK_CAM ,  24,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_CAM1",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,	20,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_CAM0",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,	16,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_FIMC3_LCLK",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,  12,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_FIMC2_LCLK",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,  8,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_FIMC1_LCLK",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,  4,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_FIMC0_LCLK",  rCLK_SRC_CAM ,  rCLK_SRC_MASK_CAM ,  0,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_DAC",  rCLK_SRC_TV ,  rCLK_SRC_MASK_TV ,  8,  1,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MIXER",	rCLK_SRC_TV ,  rCLK_SRC_MASK_TV ,  4,  1,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_HDMI",  rCLK_SRC_TV ,  rCLK_SRC_MASK_TV ,  0,  1,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MFC",  rCLK_SRC_MFC ,  rCLK_MUX_STAT_MFC ,  8,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_MFC_1",	rCLK_SRC_MFC ,	rCLK_MUX_STAT_MFC ,  4,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_MFC_0",	rCLK_SRC_MFC ,	rCLK_MUX_STAT_MFC ,  0,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G3D",  rCLK_SRC_G3D ,  rCLK_MUX_STAT_G3D ,  8,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G3D_1",	rCLK_SRC_G3D ,	rCLK_MUX_STAT_G3D ,  4,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G3D_0",	rCLK_SRC_G3D ,	rCLK_MUX_STAT_G3D ,  0,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G2D",  rCLK_SRC_IMAGE ,	rCLK_MUX_STAT_IMAGE ,  8,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G2D_1",	rCLK_SRC_IMAGE ,  rCLK_MUX_STAT_IMAGE ,  4,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_G2D_0",	rCLK_SRC_IMAGE ,  rCLK_MUX_STAT_IMAGE ,  0,  1,  SYSC_DMUX,  SYSC_NOTEST },
	{ "MUX_MIPI0",	rCLK_SRC_LCD0 ,  rCLK_SRC_MASK_LCD0 ,  12,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MDNIE_PWM0",  rCLK_SRC_LCD0 ,  rCLK_SRC_MASK_LCD0 ,	8,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MDNIE0",  rCLK_SRC_LCD0 ,  rCLK_SRC_MASK_LCD0 ,	4,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_FIMD0",	rCLK_SRC_LCD0 ,  rCLK_SRC_MASK_LCD0 ,  0,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_MIPI1",	rCLK_SRC_LCD1 ,  rCLK_SRC_MASK_LCD1 ,  12,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MDNIE_PWM1",  rCLK_SRC_LCD1 ,  rCLK_SRC_MASK_LCD1 ,	8,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MDNIE1",  rCLK_SRC_LCD1 ,  rCLK_SRC_MASK_LCD1 ,	4,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_FIMD1",	rCLK_SRC_LCD1 ,  rCLK_SRC_MASK_LCD1 ,  0,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_AUDIO0",  rCLK_SRC_MAUDIO ,	rCLK_SRC_MASK_MAUDIO ,	0,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_SATA",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  24,  1,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MMC4",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  16,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_MMC3",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  12,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_MMC2",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  8,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MMC1",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  4,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_MMC0",  rCLK_SRC_FSYS ,	rCLK_SRC_MASK_FSYS ,  0,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_PWM",  rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  24,  15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_UART5",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  20,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_UART4",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  16,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_UART3",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  12,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_UART2",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  8,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_UART1",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  4,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_UART0",	rCLK_SRC_PERIL0 ,  rCLK_SRC_MASK_PERIL0 ,  0,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_SPI3",  rCLK_SRC_PERIL1 ,  rCLK_SRC_MASK_PERIL1 ,  28,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_SPI2",  rCLK_SRC_PERIL1 ,  rCLK_SRC_MASK_PERIL1 ,  24,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_SPI1",  rCLK_SRC_PERIL1 ,  rCLK_SRC_MASK_PERIL1 ,  20,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_SPI0",  rCLK_SRC_PERIL1 ,  rCLK_SRC_MASK_PERIL1 ,  16,  15,	SYSC_NMUX,	SYSC_NOTEST },
	{ "MUX_SPDIF",	rCLK_SRC_PERIL1 ,  rCLK_SRC_MASK_PERIL1 ,  8,  3,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_AUDIO2",  rCLK_SRC_PERIL1 ,	rCLK_SRC_MASK_PERIL1 ,	4,	15,  SYSC_NMUX,  SYSC_NOTEST },
	{ "MUX_AUDIO1",  rCLK_SRC_PERIL1 ,	rCLK_SRC_MASK_PERIL1 ,	0,	15,  SYSC_NMUX,  SYSC_NOTEST },

	{ "MUX_PWI",  rCLK_SRC_CORE ,  rCLK_SRC_MASK_CORE ,  16,  15,  SYSC_NMUX,  SYSC_TEST },
	{ "MUX_CORE_TIMERS",  rCLK_SRC_CORE ,  rCLK_MUX_STAT_CORE ,  12,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_DPHY",  rCLK_SRC_CORE ,	rCLK_MUX_STAT_CORE ,  8,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_CORE_BUS",  rCLK_SRC_CORE ,	rCLK_MUX_STAT_CORE ,  4,  1,  SYSC_DMUX,  SYSC_TEST },

	{ "MUX_HPM",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,  20,	1,	SYSC_DMUX,	SYSC_TEST },
	{ "MUX_CORE",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,	16,  1,  SYSC_DMUX,  SYSC_TEST },
	{ "MUX_MPLLFOUT",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,	12,  1,  SYSC_NMUX,  SYSC_NOTEST },		// hidden spec (will be removed from manual & code)
	{ "MUX_MPLL",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,	8,	1,	SYSC_DMUX,	SYSC_TEST },
	{ "MUX_APLLFOUT",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,	4,	1,	SYSC_NMUX,	SYSC_NOTEST },		// hidden spec (will be removed from manual & code)
	{ "MUX_APLL",  rCLK_SRC_CPU ,  rCLK_MUX_STAT_CPU ,	0,	1,	SYSC_DMUX,	SYSC_TEST },
	{ "NULL", 0, 0, 0, 0, 0, SYSC_NOTEST}
};

typedef struct tag_DIV_RATIO
{	
	char strName[30];
	u32 uSetAddr;
	u32 uMonAddr;
	u32 uOffset;
	u32 uMaskBit;
	bool bUse;
} oDIV_RATIO;

static oDIV_RATIO aoDivRatio[]=
{
	{ "DIV_GPL",  rCLK_DIV_LEFTBUS ,  rCLK_DIV_STAT_LEFTBUS ,  4,  7,  SYSC_TEST },
	{ "DIV_GDL",  rCLK_DIV_LEFTBUS ,  rCLK_DIV_STAT_LEFTBUS ,  0,  7,  SYSC_TEST },
	{ "DIV_GPR",  rCLK_DIV_RIGHTBUS ,  rCLK_DIV_STAT_RIGHTBUS ,  4,  7,  SYSC_TEST },
	{ "DIV_GDR",  rCLK_DIV_RIGHTBUS ,  rCLK_DIV_STAT_RIGHTBUS ,  0,  7,  SYSC_TEST },

	{ "DIV_ONENAND",  rCLK_DIV_TOP ,  rCLK_DIV_STAT_TOP ,  16,	7,	SYSC_NOTEST },
	{ "DIV_ACLK_133",  rCLK_DIV_TOP ,  rCLK_DIV_STAT_TOP ,	12,  7,  SYSC_TEST },
	{ "DIV_ACLK_160",  rCLK_DIV_TOP ,  rCLK_DIV_STAT_TOP ,	8,	7,	SYSC_TEST },
	{ "DIV_ACLK_100",  rCLK_DIV_TOP ,  rCLK_DIV_STAT_TOP ,	4,	15,  SYSC_TEST },
	{ "DIV_ACLK_200",  rCLK_DIV_TOP ,  rCLK_DIV_STAT_TOP ,	0,	7,	SYSC_TEST },

	{ "DIV_CSIS1",	rCLK_DIV_CAM ,	rCLK_DIV_STAT_CAM ,  28,  15,  SYSC_NOTEST },
	{ "DIV_CSIS0",	rCLK_DIV_CAM ,	rCLK_DIV_STAT_CAM ,  24,  15,  SYSC_NOTEST },
	{ "DIV_CAM1",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,	20,  15,  SYSC_NOTEST },
	{ "DIV_CAM0",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,	16,  15,  SYSC_NOTEST },
	{ "DIV_FIMC3_LCLK",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,  12,  15,	SYSC_NOTEST },
	{ "DIV_FIMC2_LCLK",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,  8,  15,  SYSC_NOTEST },
	{ "DIV_FIMC1_LCLK",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,  4,  15,  SYSC_NOTEST },
	{ "DIV_FIMC0_LCLK",  rCLK_DIV_CAM ,  rCLK_DIV_STAT_CAM ,  0,  15,  SYSC_NOTEST },
	{ "DIV_TV_BLK",  rCLK_DIV_TV ,	rCLK_DIV_STAT_TV ,	0,	15,  SYSC_NOTEST },
	{ "DIV_MFC",  rCLK_DIV_MFC ,  rCLK_DIV_STAT_MFC ,  0,  15,	SYSC_NOTEST },
	{ "DIV_G3D",  rCLK_DIV_G3D ,  rCLK_DIV_STAT_G3D ,  0,  15,	SYSC_NOTEST },
	{ "DIV_G2D",  rCLK_DIV_IMAGE ,	rCLK_DIV_STAT_IMAGE ,  0,  15,	SYSC_NOTEST },
	{ "DIV_MIPI0_PRE",	rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,  20,	15,  SYSC_NOTEST },
	{ "DIV_MIPI0",	rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,  16,	15,  SYSC_NOTEST },
	{ "DIV_MDNIE_PWM0_PRE",  rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,	12,  15,  SYSC_NOTEST },
	{ "DIV_MDNIE_PWM0",  rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,	8,	15,  SYSC_NOTEST },
	{ "DIV_MDNIE0",  rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,	4,	15,  SYSC_NOTEST },
	{ "DIV_FIMD0",	rCLK_DIV_LCD0 ,  rCLK_DIV_STAT_LCD0 ,  0,  15,	SYSC_NOTEST },
	{ "DIV_MIPI1_PRE",	rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,  20,	15,  SYSC_NOTEST },
	{ "DIV_MIPI1",	rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,  16,	15,  SYSC_NOTEST },
	{ "DIV_MDNIE_PWM1_PRE",  rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,	12,  15,  SYSC_NOTEST },
	{ "DIV_MDNIE_PWM1",  rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,	8,	15,  SYSC_NOTEST },
	{ "DIV_MDNIE1",  rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,	4,	15,  SYSC_NOTEST },
	{ "DIV_FIMD1",	rCLK_DIV_LCD1 ,  rCLK_DIV_STAT_LCD1 ,  0,  15,	SYSC_NOTEST },
	{ "DIV_PCM0",  rCLK_DIV_MAUDIO ,  rCLK_DIV_STAT_MAUDIO ,  4,  255,	SYSC_NOTEST },
	{ "DIV_AUDIO0",  rCLK_DIV_MAUDIO ,	rCLK_DIV_STAT_MAUDIO ,	0,	15,  SYSC_NOTEST },
	{ "DIV_SATA",  rCLK_DIV_FSYS0 ,  rCLK_DIV_STAT_FSYS0 ,	20,  15,  SYSC_NOTEST },
	{ "DIV_MMC1_PRE",  rCLK_DIV_FSYS1 ,  rCLK_DIV_STAT_FSYS1 ,	24,  255,  SYSC_NOTEST },
	{ "DIV_MMC1",  rCLK_DIV_FSYS1 ,  rCLK_DIV_STAT_FSYS1 ,	16,  15,  SYSC_NOTEST },
	{ "DIV_MMC0_PRE",  rCLK_DIV_FSYS1 ,  rCLK_DIV_STAT_FSYS1 ,	8,	255,  SYSC_NOTEST },
	{ "DIV_MMC0",  rCLK_DIV_FSYS1 ,  rCLK_DIV_STAT_FSYS1 ,	0,	15,  SYSC_NOTEST },
	{ "DIV_MMC3_PRE",  rCLK_DIV_FSYS2 ,  rCLK_DIV_STAT_FSYS2 ,	24,  255,  SYSC_NOTEST },
	{ "DIV_MMC3",  rCLK_DIV_FSYS2 ,  rCLK_DIV_STAT_FSYS2 ,	16,  15,  SYSC_NOTEST },
	{ "DIV_MMC2_PRE",  rCLK_DIV_FSYS2 ,  rCLK_DIV_STAT_FSYS2 ,	8,	255,  SYSC_NOTEST },
	{ "DIV_MMC2",  rCLK_DIV_FSYS2 ,  rCLK_DIV_STAT_FSYS2 ,	0,	15,  SYSC_NOTEST },
	{ "DIV_MMC4_PRE",  rCLK_DIV_FSYS3 ,  rCLK_DIV_STAT_FSYS3 ,	8,	255,  SYSC_NOTEST },
	{ "DIV_MMC4",  rCLK_DIV_FSYS3 ,  rCLK_DIV_STAT_FSYS3 ,	0,	15,  SYSC_NOTEST },
	{ "DIV_UART5",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  20,	15,  SYSC_NOTEST },
	{ "DIV_UART4",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  16,	15,  SYSC_NOTEST },
	{ "DIV_UART3",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  12,	15,  SYSC_NOTEST },
	{ "DIV_UART2",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  8,  15,	SYSC_NOTEST },
	{ "DIV_UART1",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  4,  15,	SYSC_NOTEST },
	{ "DIV_UART0",	rCLK_DIV_PERIL0 ,  rCLK_DIV_STAT_PERIL0 ,  0,  15,	SYSC_NOTEST },
	{ "DIV_SPI1_PRE",  rCLK_DIV_PERIL1 ,  rCLK_DIV_STAT_PERIL1 ,  24,  255,  SYSC_NOTEST },
	{ "DIV_SPI1",  rCLK_DIV_PERIL1 ,  rCLK_DIV_STAT_PERIL1 ,  16,  15,	SYSC_NOTEST },
	{ "DIV_SPI0_PRE",  rCLK_DIV_PERIL1 ,  rCLK_DIV_STAT_PERIL1 ,  8,  255,	SYSC_NOTEST },
	{ "DIV_SPI0",  rCLK_DIV_PERIL1 ,  rCLK_DIV_STAT_PERIL1 ,  0,  15,  SYSC_NOTEST },
	{ "DIV_SPI3_PRE",  rCLK_DIV_PERIL2 ,  rCLK_DIV_STAT_PERIL2 ,  24,  255,  SYSC_NOTEST },
	{ "DIV_SPI3",  rCLK_DIV_PERIL2 ,  rCLK_DIV_STAT_PERIL2 ,  16,  15,	SYSC_NOTEST },
	{ "DIV_SPI2_PRE",  rCLK_DIV_PERIL2 ,  rCLK_DIV_STAT_PERIL2 ,  8,  255,	SYSC_NOTEST },
	{ "DIV_SPI2",  rCLK_DIV_PERIL2 ,  rCLK_DIV_STAT_PERIL2 ,  0,  15,  SYSC_NOTEST },
	{ "DIV_SLIMBUS",  rCLK_DIV_PERIL3 ,  rCLK_DIV_STAT_PERIL3 ,  4,  15,  SYSC_NOTEST },	// 4/30 RTL modified (3bit div -> 4bit div)
	{ "DIV_PWM",  rCLK_DIV_PERIL3 ,  rCLK_DIV_STAT_PERIL3 ,  0,  15,  SYSC_NOTEST },
	{ "DIV_PCM2",  rCLK_DIV_PERIL4 ,  rCLK_DIV_STAT_PERIL4 ,  20,  255,  SYSC_NOTEST },
	{ "DIV_AUDIO2",  rCLK_DIV_PERIL4 ,	rCLK_DIV_STAT_PERIL4 ,	16,  15,  SYSC_NOTEST },
	{ "DIV_PCM1",  rCLK_DIV_PERIL4 ,  rCLK_DIV_STAT_PERIL4 ,  4,  255,	SYSC_NOTEST },
	{ "DIV_AUDIO1",  rCLK_DIV_PERIL4 ,	rCLK_DIV_STAT_PERIL4 ,	0,	15,  SYSC_NOTEST },
	{ "DIV_I2S2",  rCLK_DIV_PERIL5 ,  rCLK_DIV_STAT_PERIL5 ,  8,  63,  SYSC_NOTEST },
	{ "DIV_I2S1",  rCLK_DIV_PERIL5 ,  rCLK_DIV_STAT_PERIL5 ,  0,  63,  SYSC_NOTEST },
	{ "DIV2_GPS_BLK",  rCLKDIV2_RATIO ,	rCLKDIV2_STAT ,  24,  3,  SYSC_NOTEST },
	{ "DIV2_TV_BLK",  rCLKDIV2_RATIO ,  rCLKDIV2_STAT ,	20,  3,  SYSC_NOTEST },
	{ "DIV2_LCD1_BLK",  rCLKDIV2_RATIO ,  rCLKDIV2_STAT ,  16,  3,  SYSC_NOTEST },
	{ "DIV2_LCD0_BLK",  rCLKDIV2_RATIO ,  rCLKDIV2_STAT ,  12,  3,  SYSC_NOTEST },
	{ "DIV2_IMG_BLK",  rCLKDIV2_RATIO ,	rCLKDIV2_STAT ,  8,  3,  SYSC_NOTEST },
	{ "DIV2_CAM_BLK",  rCLKDIV2_RATIO ,	rCLKDIV2_STAT ,  4,  3,  SYSC_NOTEST },
	{ "DIV2_FSYS_BLK",  rCLKDIV2_RATIO ,  rCLKDIV2_STAT ,  0,  3,  SYSC_NOTEST },

	{ "DIV_CORE_TIMERS",  rCLK_DIV_CORE0 ,	rCLK_DIV_STAT_CORE0 ,  28,	7,	SYSC_TEST },
	{ "DIV_COPY2",	rCLK_DIV_CORE0 ,  rCLK_DIV_STAT_CORE0 ,  24,  7,  SYSC_TEST },
	{ "DIV_COREP",	rCLK_DIV_CORE0 ,  rCLK_DIV_STAT_CORE0 ,  20,  7,  SYSC_TEST },
	{ "DIV_CORED",	rCLK_DIV_CORE0 ,  rCLK_DIV_STAT_CORE0 ,  16,  7,  SYSC_TEST },
	{ "DIV_DMC",  rCLK_DIV_CORE0 ,	rCLK_DIV_STAT_CORE0 ,  12,	7,	SYSC_TEST },
	{ "DIV_DPHY",  rCLK_DIV_CORE0 ,  rCLK_DIV_STAT_CORE0 ,	8,	7,	SYSC_TEST },
	{ "DIV_ACP_PCLK",  rCLK_DIV_CORE0 ,  rCLK_DIV_STAT_CORE0 ,	4,	7,	SYSC_TEST },
	{ "DIV_ACP",  rCLK_DIV_CORE0 ,	rCLK_DIV_STAT_CORE0 ,  0,  7,  SYSC_TEST },
	{ "DIV_DPM",  rCLK_DIV_CORE1 ,	rCLK_DIV_STAT_CORE1 ,  24,	127,  SYSC_TEST },
	{ "DIV_DVSEM",	rCLK_DIV_CORE1 ,  rCLK_DIV_STAT_CORE1 ,  16,  127,	SYSC_TEST },
	{ "DIV_PWI",  rCLK_DIV_CORE1 ,	rCLK_DIV_STAT_CORE1 ,  8,  15,	SYSC_TEST },

	{ "DIV_APLL",  rCLK_DIV_CPU0 ,	rCLK_DIV_STAT_CPU0 ,  24,  7,  SYSC_TEST },
	{ "DIV_PCLK_DBG",  rCLK_DIV_CPU0 ,	rCLK_DIV_STAT_CPU0 ,  20,  7,  SYSC_TEST },
	{ "DIV_ATB",  rCLK_DIV_CPU0 ,  rCLK_DIV_STAT_CPU0 ,  16,  7,  SYSC_TEST },
	{ "DIV_PERIPH",  rCLK_DIV_CPU0 ,  rCLK_DIV_STAT_CPU0 ,	12,  7,  SYSC_TEST },
	{ "DIV_COREM1",  rCLK_DIV_CPU0 ,  rCLK_DIV_STAT_CPU0 ,	8,	7,	SYSC_TEST },
	{ "DIV_COREM0",  rCLK_DIV_CPU0 ,  rCLK_DIV_STAT_CPU0 ,	4,	7,	SYSC_TEST },
	{ "DIV_CORE",  rCLK_DIV_CPU0 ,	rCLK_DIV_STAT_CPU0 ,  0,  7,  SYSC_TEST },
	{ "DIV_HPM",  rCLK_DIV_CPU1 ,  rCLK_DIV_STAT_CPU1 ,  4,  7,  SYSC_TEST },
	{ "DIV_COPY",  rCLK_DIV_CPU1 ,	rCLK_DIV_STAT_CPU1 ,  0,  7,  SYSC_TEST },

	{ "NULL", 0, 0, 0, 0, SYSC_NOTEST}
};

typedef struct tag_GATE_IP
{	
	char strName[30];
	u32 uSetAddr;
	u32 uOffset;
	u32 uMaskBit;
	bool bUse;
} oGATE_IP;

static oGATE_IP aoGateIp[]=
{
	{ "GATE_IP_PPMULEFT",  rCLK_GATE_IP_LEFTBUS ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMURIGHT",	rCLK_GATE_IP_RIGHTBUS ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_PIXELASYNCM1",  rCLK_GATE_IP_CAM ,  18,	1,	SYSC_NOTEST },
	{ "GATE_IP_PIXELASYNCM0",  rCLK_GATE_IP_CAM ,  17,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUCAMIF",	rCLK_GATE_IP_CAM ,	16,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEFIMC3",  rCLK_GATE_IP_CAM ,  15,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEFIMC2",  rCLK_GATE_IP_CAM ,  14,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEFIMC1",  rCLK_GATE_IP_CAM ,  13,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEFIMC0",  rCLK_GATE_IP_CAM ,  12,  1,  SYSC_NOTEST },
	{ "GATE_IP_SMMUJPEG",  rCLK_GATE_IP_CAM ,  11,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMC3",	rCLK_GATE_IP_CAM ,	10,  1,  SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMC2",	rCLK_GATE_IP_CAM ,	9,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMC1",	rCLK_GATE_IP_CAM ,	8,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMC0",	rCLK_GATE_IP_CAM ,	7,	1,	SYSC_NOTEST },
	{ "GATE_IP_JPEG",  rCLK_GATE_IP_CAM ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_CSIS1",	rCLK_GATE_IP_CAM ,	5,	1,	SYSC_NOTEST },
	{ "GATE_IP_CSIS0",	rCLK_GATE_IP_CAM ,	4,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMC3",	rCLK_GATE_IP_CAM ,	3,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMC2",	rCLK_GATE_IP_CAM ,	2,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMC1",	rCLK_GATE_IP_CAM ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMC0",	rCLK_GATE_IP_CAM ,	0,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUTV",  rCLK_GATE_IP_TV ,	5,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUTV",  rCLK_GATE_IP_TV ,	4,	1,	SYSC_NOTEST },
	{ "GATE_IP_HDMI",  rCLK_GATE_IP_TV ,  3,  1,  SYSC_NOTEST },
	{ "GATE_IP_TVENC",	rCLK_GATE_IP_TV ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_MIXER",	rCLK_GATE_IP_TV ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_VP",  rCLK_GATE_IP_TV ,	0,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUMFC_R",	rCLK_GATE_IP_MFC ,	4,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUMFC_L",	rCLK_GATE_IP_MFC ,	3,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUMFC_R",	rCLK_GATE_IP_MFC ,	2,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUMFC_L",	rCLK_GATE_IP_MFC ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_MFC",  rCLK_GATE_IP_MFC ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMUG3D",  rCLK_GATE_IP_G3D ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_G3D",  rCLK_GATE_IP_G3D ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMUIMAGE",	rCLK_GATE_IP_IMAGE ,  9,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEMDMA2",  rCLK_GATE_IP_IMAGE ,	8,	1,	SYSC_NOTEST },
	{ "GATE_IP_QEROTATOR",	rCLK_GATE_IP_IMAGE ,  7,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEG2D",	rCLK_GATE_IP_IMAGE ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_SMMUMDMA2",	rCLK_GATE_IP_IMAGE ,  5,  1,  SYSC_NOTEST },
	{ "GATE_IP_SMMUROTATOR",  rCLK_GATE_IP_IMAGE ,	4,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUG2D",  rCLK_GATE_IP_IMAGE ,	3,	1,	SYSC_NOTEST },
	{ "GATE_IP_MDMA2",	rCLK_GATE_IP_IMAGE ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_ROTATOR",  rCLK_GATE_IP_IMAGE ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_G2D",  rCLK_GATE_IP_IMAGE ,	0,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMULCD0",  rCLK_GATE_IP_LCD0 ,	5,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMD0",	rCLK_GATE_IP_LCD0 ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_DSIM0",	rCLK_GATE_IP_LCD0 ,  3,  1,  SYSC_NOTEST },
	{ "GATE_IP_MDNIE0",  rCLK_GATE_IP_LCD0 ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_MIE0",  rCLK_GATE_IP_LCD0 ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMD0",	rCLK_GATE_IP_LCD0 ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMULCD1",  rCLK_GATE_IP_LCD1 ,	5,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUFIMD1",	rCLK_GATE_IP_LCD1 ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_DSIM1",	rCLK_GATE_IP_LCD1 ,  3,  1,  SYSC_NOTEST },
	{ "GATE_IP_MDNIE1",  rCLK_GATE_IP_LCD1 ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_MIE1",  rCLK_GATE_IP_LCD1 ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_FIMD1",	rCLK_GATE_IP_LCD1 ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMUPCIE",  rCLK_GATE_IP_FSYS ,	18,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMUFILE",  rCLK_GATE_IP_FSYS ,	17,  1,  SYSC_NOTEST },
	{ "GATE_IP_NFCON",	rCLK_GATE_IP_FSYS ,  16,  1,  SYSC_NOTEST },
	{ "GATE_IP_ONENAND",  rCLK_GATE_IP_FSYS ,  15,	1,	SYSC_NOTEST },
	{ "GATE_IP_PCIE",  rCLK_GATE_IP_FSYS ,	14,  1,  SYSC_NOTEST },
	{ "GATE_IP_USBOTG",  rCLK_GATE_IP_FSYS ,  13,  1,  SYSC_NOTEST },
	{ "GATE_IP_USBHOST",  rCLK_GATE_IP_FSYS ,  12,	1,	SYSC_NOTEST },
	{ "GATE_IP_SROMC",	rCLK_GATE_IP_FSYS ,  11,  1,  SYSC_NOTEST },
	{ "GATE_IP_SATA",  rCLK_GATE_IP_FSYS ,	10,  1,  SYSC_NOTEST },
	{ "GATE_IP_SDMMC4",  rCLK_GATE_IP_FSYS ,  9,  1,  SYSC_NOTEST },
	{ "GATE_IP_SDMMC3",  rCLK_GATE_IP_FSYS ,  8,  1,  SYSC_NOTEST },
	{ "GATE_IP_SDMMC2",  rCLK_GATE_IP_FSYS ,  7,  1,  SYSC_NOTEST },
	{ "GATE_IP_SDMMC1",  rCLK_GATE_IP_FSYS ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_SDMMC0",  rCLK_GATE_IP_FSYS ,  5,  1,  SYSC_NOTEST },
	{ "GATE_IP_TSI",  rCLK_GATE_IP_FSYS ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_SATAPHY",  rCLK_GATE_IP_FSYS ,  3,  1,  SYSC_NOTEST },
	{ "GATE_IP_PCIEPHY",  rCLK_GATE_IP_FSYS ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_PDMA1",	rCLK_GATE_IP_FSYS ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_PDMA0",	rCLK_GATE_IP_FSYS ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_SMMUGPS",  rCLK_GATE_IP_GPS ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_GPS",  rCLK_GATE_IP_GPS ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_MODEMIF",  rCLK_GATE_IP_PERIL ,	28,  1,  SYSC_NOTEST },
	{ "GATE_IP_AC97",  rCLK_GATE_IP_PERIL ,  27,  1,  SYSC_NOTEST },
	{ "GATE_IP_SPDIF",	rCLK_GATE_IP_PERIL ,  26,  1,  SYSC_NOTEST },
	{ "GATE_IP_SLIMBUS",  rCLK_GATE_IP_PERIL ,	25,  1,  SYSC_NOTEST },
	{ "GATE_IP_PWM",  rCLK_GATE_IP_PERIL ,	24,  1,  SYSC_NOTEST },
	{ "GATE_IP_PCM2",  rCLK_GATE_IP_PERIL ,  23,  1,  SYSC_NOTEST },
	{ "GATE_IP_PCM1",  rCLK_GATE_IP_PERIL ,  22,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2S2",  rCLK_GATE_IP_PERIL ,  21,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2S1",  rCLK_GATE_IP_PERIL ,  20,  1,  SYSC_NOTEST },
	{ "GATE_IP_SPI3",  rCLK_GATE_IP_PERIL ,  19,  1,  SYSC_NOTEST },
	{ "GATE_IP_SPI2",  rCLK_GATE_IP_PERIL ,  18,  1,  SYSC_NOTEST },
	{ "GATE_IP_SPI1",  rCLK_GATE_IP_PERIL ,  17,  1,  SYSC_NOTEST },
	{ "GATE_IP_SPI0",  rCLK_GATE_IP_PERIL ,  16,  1,  SYSC_NOTEST },
	{ "GATE_IP_TSADC",	rCLK_GATE_IP_PERIL ,  15,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2CHDMI",  rCLK_GATE_IP_PERIL ,	14,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C7",  rCLK_GATE_IP_PERIL ,  13,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C6",  rCLK_GATE_IP_PERIL ,  12,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C5",  rCLK_GATE_IP_PERIL ,  11,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C4",  rCLK_GATE_IP_PERIL ,  10,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C3",  rCLK_GATE_IP_PERIL ,  9,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C2",  rCLK_GATE_IP_PERIL ,  8,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C1",  rCLK_GATE_IP_PERIL ,  7,  1,  SYSC_NOTEST },
	{ "GATE_IP_I2C0",  rCLK_GATE_IP_PERIL ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART5",	rCLK_GATE_IP_PERIL ,  5,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART4",	rCLK_GATE_IP_PERIL ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART3",	rCLK_GATE_IP_PERIL ,  3,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART2",	rCLK_GATE_IP_PERIL ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART1",	rCLK_GATE_IP_PERIL ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_UART0",	rCLK_GATE_IP_PERIL ,  0,  1,  SYSC_NOTEST },
	{ "GATE_IP_KEYIF",	rCLK_GATE_IP_PERIR ,  16,  1,  SYSC_NOTEST },
	{ "GATE_IP_RTC",  rCLK_GATE_IP_PERIR ,	15,  1,  SYSC_NOTEST },
	{ "GATE_IP_WDT",  rCLK_GATE_IP_PERIR ,	14,  1,  SYSC_NOTEST },
	{ "GATE_IP_ST",  rCLK_GATE_IP_PERIR ,  13,	1,	SYSC_NOTEST },
	{ "GATE_IP_SECKEY",  rCLK_GATE_IP_PERIR ,  12,	1,	SYSC_NOTEST },
	{ "GATE_IP_HDMI_CEC",  rCLK_GATE_IP_PERIR ,  11,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC5",	rCLK_GATE_IP_PERIR ,  10,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC4",	rCLK_GATE_IP_PERIR ,  9,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC3",	rCLK_GATE_IP_PERIR ,  8,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC2",	rCLK_GATE_IP_PERIR ,  7,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC1",	rCLK_GATE_IP_PERIR ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_TZPC0",	rCLK_GATE_IP_PERIR ,  5,  1,  SYSC_NOTEST },
	{ "GATE_IP_CMU_COREPART",  rCLK_GATE_IP_PERIR ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_CMU_TOPPART",  rCLK_GATE_IP_PERIR ,	3,	1,	SYSC_NOTEST },
	{ "GATE_IP_PMU_APBIF",	rCLK_GATE_IP_PERIR ,  2,  1,  SYSC_NOTEST },
	{ "GATE_IP_SYSREG",  rCLK_GATE_IP_PERIR ,  1,  1,  SYSC_NOTEST },
	{ "GATE_IP_CHIP_ID",  rCLK_GATE_IP_PERIR ,	0,	1,	SYSC_NOTEST },
	{ "GATE_IP_GIC",  rCLK_GATE_IP_CORE ,  20,	1,	SYSC_NOTEST },
	{ "GATE_IP_CORE_TIMERS",  rCLK_GATE_IP_CORE ,  19,	1,	SYSC_NOTEST },
	{ "GATE_IP_IEM_IEC",  rCLK_GATE_IP_CORE ,  18,	1,	SYSC_NOTEST },
	{ "GATE_IP_IEM_APC",  rCLK_GATE_IP_CORE ,  17,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUACP",  rCLK_GATE_IP_CORE ,  16,	1,	SYSC_NOTEST },
	{ "GATE_IP_QESSS",	rCLK_GATE_IP_CORE ,  15,  1,  SYSC_NOTEST },
	{ "GATE_IP_QEMDMA",  rCLK_GATE_IP_CORE ,  14,  1,  SYSC_NOTEST },
	{ "GATE_IP_ID_REMAPPER",  rCLK_GATE_IP_CORE ,  13,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUSSS",  rCLK_GATE_IP_CORE ,  12,	1,	SYSC_NOTEST },
	{ "GATE_IP_SMMUMDMA",  rCLK_GATE_IP_CORE ,	11,  1,  SYSC_NOTEST },
	{ "GATE_IP_PPMUCPU",  rCLK_GATE_IP_CORE ,  10,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUDMC1",  rCLK_GATE_IP_CORE ,	9,	1,	SYSC_NOTEST },
	{ "GATE_IP_PPMUDMC0",  rCLK_GATE_IP_CORE ,	8,	1,	SYSC_NOTEST },
	{ "GATE_IP_QECPU",	rCLK_GATE_IP_CORE ,  7,  1,  SYSC_NOTEST },
	{ "GATE_IP_SECJTAG",  rCLK_GATE_IP_CORE ,  6,  1,  SYSC_NOTEST },
	{ "GATE_IP_SSS",  rCLK_GATE_IP_CORE ,  4,  1,  SYSC_NOTEST },
	{ "GATE_IP_MDMA",  rCLK_GATE_IP_CORE ,	3,	1,	SYSC_NOTEST },
	{ "GATE_IP_INT_COMB",  rCLK_GATE_IP_CORE ,	2,	1,	SYSC_NOTEST },
	{ "GATE_IP_DMC1",  rCLK_GATE_IP_CORE ,	1,	1,	SYSC_NOTEST },
	{ "GATE_IP_DMC0",  rCLK_GATE_IP_CORE ,	0,	1,	SYSC_NOTEST },
	{ "NULL", 0, 0, 0, SYSC_NOTEST}
};

typedef struct tag_GATE_BLK
{	
	char strName[30];
	u32 uSetAddr;
	u32 uOffset;
	u32 uMaskBit;
	bool bUse;
} oGATE_BLK;

static oGATE_BLK aoGateBlk[]=
{
	{ "GATE_BLK_LCD1",  rCLK_GATE_BLOCK ,  5,  1,  SYSC_NOTEST },
	{ "GATE_BLK_LCD0",  rCLK_GATE_BLOCK ,  4,  1,  SYSC_NOTEST },
	{ "GATE_BLK_G3D",  rCLK_GATE_BLOCK ,  3,  1,  SYSC_NOTEST },
	{ "GATE_BLK_MFC",  rCLK_GATE_BLOCK ,  2,  1,  SYSC_NOTEST },
	{ "GATE_BLK_TV",  rCLK_GATE_BLOCK ,	1,	1,	SYSC_NOTEST },
	{ "GATE_BLK_CAM",  rCLK_GATE_BLOCK ,  0,  1,  SYSC_NOTEST },
	{ "NULL", 0, 0, 0, SYSC_NOTEST}
};

typedef struct tag_CLK_OUT
{	
	char strName[50];
	u32 uSetAddr;
	u32 uClkOutMuxVal;
	bool bUse;
} oCLK_OUT;

static oCLK_OUT aoClkOut[]=
{
	{ "CLKOUT_LEFTBUS_SCLK_MPLL_2", rCLKOUT_CMU_LEFTBUS, 0, SYSC_TEST },
	{ "CLKOUT_LEFTBUS_SCLK_APLL_2", rCLKOUT_CMU_LEFTBUS, 1, SYSC_TEST },
	{ "CLKOUT_LEFTBUS_ACLK_GDL", rCLKOUT_CMU_LEFTBUS, 2, SYSC_TEST },
	{ "CLKOUT_LEFTBUS_ACLK_GPL", rCLKOUT_CMU_LEFTBUS, 3, SYSC_TEST },

	{ "CLKOUT_RIGHTBUS_SCLK_MPLL_2", rCLKOUT_CMU_RIGHTBUS, 0, SYSC_TEST },
	{ "CLKOUT_RIGHTBUS_SCLK_APLL_2", rCLKOUT_CMU_RIGHTBUS, 1, SYSC_TEST },
	{ "CLKOUT_RIGHTBUS_ACLK_GDR", rCLKOUT_CMU_RIGHTBUS, 2, SYSC_TEST },
	{ "CLKOUT_RIGHTBUS_ACLK_GPR", rCLKOUT_CMU_RIGHTBUS, 3, SYSC_TEST },

	{ "CLKOUT_TOP_EPLL_FOUT", rCLKOUT_CMU_TOP, 0, SYSC_TEST },
	{ "CLKOUT_TOP_VPLL_FOUT", rCLKOUT_CMU_TOP, 1, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_HDMI27M", rCLKOUT_CMU_TOP, 2, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_USBPHY0", rCLKOUT_CMU_TOP, 3, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_USBPHY1", rCLKOUT_CMU_TOP, 4, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_HDMIPHY", rCLKOUT_CMU_TOP, 5, SYSC_TEST },
	{ "CLKOUT_TOP_AUDIOCDCLK0", rCLKOUT_CMU_TOP, 6, SYSC_TEST },
	{ "CLKOUT_TOP_AUDIOCDCLK1", rCLKOUT_CMU_TOP, 7, SYSC_TEST },
	{ "CLKOUT_TOP_AUDIOCDCLK2", rCLKOUT_CMU_TOP, 8, SYSC_TEST },
	{ "CLKOUT_TOP_SPDIF_EXTCLK", rCLKOUT_CMU_TOP, 9, SYSC_TEST },
	{ "CLKOUT_TOP_ACLK_160", rCLKOUT_CMU_TOP, 10, SYSC_TEST },
	{ "CLKOUT_TOP_ACLK_133", rCLKOUT_CMU_TOP, 11, SYSC_TEST },
	{ "CLKOUT_TOP_ACLK_200", rCLKOUT_CMU_TOP, 12, SYSC_TEST },
	{ "CLKOUT_TOP_ACLK_100", rCLKOUT_CMU_TOP, 13, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_MFC", rCLKOUT_CMU_TOP, 14, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_G3D", rCLKOUT_CMU_TOP, 15, SYSC_TEST },
	{ "CLKOUT_TOP_SCLK_G2D", rCLKOUT_CMU_TOP, 16, SYSC_TEST },
	{ "CLKOUT_TOP_CAM_A_PCLK", rCLKOUT_CMU_TOP, 17, SYSC_TEST },
	{ "CLKOUT_TOP_CAM_B_PCLK", rCLKOUT_CMU_TOP, 18, SYSC_TEST },
	{ "CLKOUT_TOP_S_RXBYTECLKHS0_2L", rCLKOUT_CMU_TOP, 19, SYSC_TEST },
	{ "CLKOUT_TOP_S_RXBYTECLKHS0_4L", rCLKOUT_CMU_TOP, 20, SYSC_TEST },
	{ "CLKOUT_TOP_RX_HALF_BYTE_CLK_CSIS0", rCLKOUT_CMU_TOP, 21, SYSC_TEST },
	{ "CLKOUT_TOP_RX_HALF_BYTE_CLK_CSIS1", rCLKOUT_CMU_TOP, 22, SYSC_TEST },

	{ "CLKOUT_CORE_ACLK_CORED", rCLKOUT_CMU_CORE, 0, SYSC_TEST },
	{ "CLKOUT_CORE_ACLK_COREP", rCLKOUT_CMU_CORE, 1, SYSC_TEST },
	{ "CLKOUT_CORE_ACLK_ACP", rCLKOUT_CMU_CORE, 2, SYSC_TEST },
	{ "CLKOUT_CORE_PCLK_ACP", rCLKOUT_CMU_CORE, 3, SYSC_TEST },
	{ "CLKOUT_CORE_SCLK_DMC", rCLKOUT_CMU_CORE, 4, SYSC_TEST },
	{ "CLKOUT_CORE_SCLK_PHY", rCLKOUT_CMU_CORE, 5, SYSC_TEST },
	{ "CLKOUT_CORE_SCLK_CORE_TIMERS", rCLKOUT_CMU_CORE, 6, SYSC_TEST },
	{ "CLKOUT_CORE_SCLK_PWI", rCLKOUT_CMU_CORE, 7, SYSC_TEST },

	{ "CLKOUT_CPU_APLL_FOUT_2", rCLKOUT_CMU_CPU, 0, SYSC_TEST },
	{ "CLKOUT_CPU_APLL_VCOOUT_4", rCLKOUT_CMU_CPU, 1, SYSC_TEST },
	{ "CLKOUT_CPU_MPLL_FOUT_2", rCLKOUT_CMU_CPU, 2, SYSC_TEST },
	{ "CLKOUT_CPU_MPLL_VCOOUT_4", rCLKOUT_CMU_CPU, 3, SYSC_TEST },
	{ "CLKOUT_CPU_ARMCLK_2", rCLKOUT_CMU_CPU, 4, SYSC_TEST },
	{ "CLKOUT_CPU_ACLK_COREM0", rCLKOUT_CMU_CPU, 5, SYSC_TEST },
	{ "CLKOUT_CPU_ACLK_COREM1", rCLKOUT_CMU_CPU, 6, SYSC_TEST },
	{ "CLKOUT_CPU_ACLK_CORES", rCLKOUT_CMU_CPU, 7, SYSC_TEST },
	{ "CLKOUT_CPU_ATCLK", rCLKOUT_CMU_CPU, 8, SYSC_TEST },
	{ "CLKOUT_CPU_PERIPHCLK", rCLKOUT_CMU_CPU, 9, SYSC_TEST },
	{ "CLKOUT_CPU_PCLK_DBG", rCLKOUT_CMU_CPU, 10, SYSC_TEST },
	{ "CLKOUT_CPU_SCLK_HPM", rCLKOUT_CMU_CPU, 11, SYSC_TEST },

	{ "CLKOUT_XXTI", 0x10020a00, 8, SYSC_TEST },
	{ "CLKOUT_XUSBXTI", 0x10020a00, 9, SYSC_TEST },
	{ "CLKOUT_RTC_TICCLK", 0x10020a00, 12, SYSC_TEST },
	{ "CLKOUT_RTCCLK", 0x10020a00, 13, SYSC_TEST },
	{ "NULL", 0, 0, SYSC_NOTEST }
};

// For Pll
static float SYSC_SetPll4508(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv);
static float SYSC_SetPll4600(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv);
static float SYSC_SetPll4650(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv);

static float SYSC_GetVcoPll4508(u32 uConBaseAddr);
static float SYSC_GetVcoPll4600(u32 uConBaseAddr);
static float SYSC_GetVcoPll4650(u32 uConBaseAddr);
static float SYSC_GetFoutPll4508(u32 uConBaseAddr);
static float SYSC_GetFoutPll4600(u32 uConBaseAddr);
static float SYSC_GetFoutPll4650(u32 uConBaseAddr);

static float SYSC_CalcPll4508(u32 uPdiv, u32 uMdiv, u32 uSdiv);
static float SYSC_CalcPll4600(u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv);
static float SYSC_CalcPll4650(u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv);

// For Mux
static void SYSC_SetDeglitchMux(SYSC_MUX eMux, u32 uMuxSelVal);
static void SYSC_SetNormalMux(SYSC_MUX eMux, u32 uMuxSelVal);

// For CMU clock-out
static void SYSC_SetCmuClkOut( SYSC_CLKOUT eClkOut, u32 uDivVal );

// [Get clk mux out]
static float SYSC_GetMuxClkOut(SYSC_MUX eMux);


float SYSC_GetClkFreq(SYSC_CLK eClk)
{
	float fClk;
	switch( eClk )
	{
		case SYSC_ARMCLK:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_CORE)/SYSC_GetClkDiv(SYSC_DIV_CORE);
			break;
		case SYSC_SCLK_DMC:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_CORE_BUS)/SYSC_GetClkDiv(SYSC_DIV_DMC);
			break;
		case SYSC_ACLK_CORED:
			fClk = SYSC_GetClkFreq(SYSC_SCLK_DMC)/SYSC_GetClkDiv(SYSC_DIV_CORED);
			break;
		case SYSC_ACLK_COREP:
			fClk = SYSC_GetClkFreq(SYSC_ACLK_CORED)/SYSC_GetClkDiv(SYSC_DIV_COREP);
			break;
		case SYSC_ACLK_200:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_ACLK_200)/SYSC_GetClkDiv(SYSC_DIV_ACLK_200);
			break;
		case SYSC_ACLK_100:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_ACLK_100)/SYSC_GetClkDiv(SYSC_DIV_ACLK_100);
			break;
		case SYSC_ACLK_160:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_ACLK_160)/SYSC_GetClkDiv(SYSC_DIV_ACLK_160);
			break;
		case SYSC_ACLK_133:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_ACLK_133)/SYSC_GetClkDiv(SYSC_DIV_ACLK_133);
			break;
		case SYSC_ACLK_GDL:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_GDL)/SYSC_GetClkDiv(SYSC_DIV_GDL);
			break;
		case SYSC_ACLK_GPL:
			fClk = SYSC_GetClkFreq(SYSC_ACLK_GDL)/SYSC_GetClkDiv(SYSC_DIV_GPL);
			break;
		case SYSC_ACLK_GDR:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_GDR)/SYSC_GetClkDiv(SYSC_DIV_GDR);
			break;
		case SYSC_ACLK_GPR:
			fClk = SYSC_GetClkFreq(SYSC_ACLK_GDR)/SYSC_GetClkDiv(SYSC_DIV_GPR);
			break;
		case SYSC_XXTI:
		case SYSC_XUSBXTI:
			fClk = FIN;	break;
		case SYSC_SCLK_APLL:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL);
			break;
		case SYSC_SCLK_MPLL:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_SCLK_EPLL:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			break;
		case SYSC_SCLK_VPLL:
			fClk = SYSC_GetMuxClkOut(SYSC_MUX_VPLL);
			break;
		
		default:
			;
	}

	return fClk;
}

void SYSC_SetCpuDiv(oCPU_DIV *poCpuDiv)
{
#if 1
	Outp32( rCLK_DIV_CPU0, ((poCpuDiv->uDivApll-1) << 24)|
						   ((poCpuDiv->uDivPclkDbg-1) << 20)|
						   ((poCpuDiv->uDivAtb-1) << 16)|
						   ((poCpuDiv->uDivPeriph-1) << 12)|
						   ((poCpuDiv->uDivCoreM1-1) << 8)|
						   ((poCpuDiv->uDivCoreM0-1) << 4)|
						   (poCpuDiv->uDivCore-1) );
	Outp32( rCLK_DIV_CPU1, ((poCpuDiv->uDivHpm-1) << 4)|(poCpuDiv->uDivCopy-1) );
#else
	SYSC_SetClkDiv(SYSC_DIV_APLL, poCpuDiv->uDivApll);
	SYSC_SetClkDiv(SYSC_DIV_CORE, poCpuDiv->uDivCore);
	SYSC_SetClkDiv(SYSC_DIV_COREM0, poCpuDiv->uDivCoreM0);
	SYSC_SetClkDiv(SYSC_DIV_COREM1, poCpuDiv->uDivCoreM1);
	SYSC_SetClkDiv(SYSC_DIV_PERIPH, poCpuDiv->uDivPeriph);

	if ( poCpuDiv->uDivCopy > poCpuDiv->uDivHpm ) {
		SYSC_SetClkDiv(SYSC_DIV_COPY, poCpuDiv->uDivCopy);
		SYSC_SetClkDiv(SYSC_DIV_HPM, poCpuDiv->uDivHpm);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_HPM, poCpuDiv->uDivHpm);
		SYSC_SetClkDiv(SYSC_DIV_COPY, poCpuDiv->uDivCopy);
	}

	if ( poCpuDiv->uDivAtb > poCpuDiv->uDivPclkDbg ) {
		SYSC_SetClkDiv(SYSC_DIV_ATB, poCpuDiv->uDivAtb);
		SYSC_SetClkDiv(SYSC_DIV_PCLK_DBG, poCpuDiv->uDivPclkDbg);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_PCLK_DBG, poCpuDiv->uDivPclkDbg);
		SYSC_SetClkDiv(SYSC_DIV_ATB, poCpuDiv->uDivAtb);
	}
#endif
}

void SYSC_SetCoreDiv(oCORE_DIV *poCoreDiv)
{
	u32 uRegClkDivCore1;
#if 1
	Outp32( rCLK_DIV_CORE0, ((poCoreDiv->uDivCoreTimers-1) << 28)|
							((poCoreDiv->uDivCopy2-1) << 24)|
							((poCoreDiv->uDivCoreP-1) << 20)|
							((poCoreDiv->uDivCoreD-1) << 16)|
							((poCoreDiv->uDivDmc-1) << 12)|
							((poCoreDiv->uDivDphy-1) << 8)|
							((poCoreDiv->uDivAcpPclk-1) << 4)|
							(poCoreDiv->uDivAcp-1) );

	uRegClkDivCore1 = Inp32(rCLK_DIV_CORE1);
	uRegClkDivCore1 = ( uRegClkDivCore1 & ~(0x7f<<24) )|(poCoreDiv->uDivDpm-1 << 24);
	uRegClkDivCore1 = ( uRegClkDivCore1 & ~(0x7f<<16) )|(poCoreDiv->uDivDvsem-1 << 16);
	Outp32( rCLK_DIV_CORE1, uRegClkDivCore1 );
#else
	if ( poCoreDiv->uDivDmc > poCoreDiv->uDivCoreD) {
		SYSC_SetClkDiv(SYSC_DIV_DMC, poCoreDiv->uDivDmc);
		if ( poCoreDiv->uDivCoreD > poCoreDiv->uDivCoreP ) {
			SYSC_SetClkDiv(SYSC_DIV_CORED, poCoreDiv->uDivCoreD);
			SYSC_SetClkDiv(SYSC_DIV_COREP, poCoreDiv->uDivCoreP);
		}
		else {
			SYSC_SetClkDiv(SYSC_DIV_COREP, poCoreDiv->uDivCoreP);
			SYSC_SetClkDiv(SYSC_DIV_CORED, poCoreDiv->uDivCoreD);
		}
	}
	else {
		if ( poCoreDiv->uDivCoreD > poCoreDiv->uDivCoreP ) {
			SYSC_SetClkDiv(SYSC_DIV_CORED, poCoreDiv->uDivCoreD);
			SYSC_SetClkDiv(SYSC_DIV_COREP, poCoreDiv->uDivCoreP);
		}
		else {
			SYSC_SetClkDiv(SYSC_DIV_COREP, poCoreDiv->uDivCoreP);
			SYSC_SetClkDiv(SYSC_DIV_CORED, poCoreDiv->uDivCoreD);
		}
		SYSC_SetClkDiv(SYSC_DIV_DMC, poCoreDiv->uDivDmc);
	}

	if ( poCoreDiv->uDivAcp > poCoreDiv->uDivAcpPclk ) {
		SYSC_SetClkDiv(SYSC_DIV_ACP, poCoreDiv->uDivAcp);
		SYSC_SetClkDiv(SYSC_DIV_ACP_PCLK, poCoreDiv->uDivAcpPclk);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_ACP_PCLK, poCoreDiv->uDivAcpPclk);
		SYSC_SetClkDiv(SYSC_DIV_ACP, poCoreDiv->uDivAcp);
	}

	SYSC_SetClkDiv(SYSC_DIV_DPHY, poCoreDiv->uDivDphy);
	SYSC_SetClkDiv(SYSC_DIV_DPM, poCoreDiv->uDivDpm);
	SYSC_SetClkDiv(SYSC_DIV_DVSEM, poCoreDiv->uDivDvsem);

	if ( poCoreDiv->uDivCopy2 > poCoreDiv->uDivCoreTimers) {
		SYSC_SetClkDiv(SYSC_DIV_COPY2, poCoreDiv->uDivCopy2);
		SYSC_SetClkDiv(SYSC_DIV_CORE_TIMERS, poCoreDiv->uDivCoreTimers);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_CORE_TIMERS, poCoreDiv->uDivCoreTimers);
		SYSC_SetClkDiv(SYSC_DIV_COPY2, poCoreDiv->uDivCopy2);
	}
#endif
}

void SYSC_SetTopBusDiv(oTOPBUS_DIV *poTopBusDiv)
{
#if 1
	u32 uRegClkDivTop;

	uRegClkDivTop = Inp32( rCLK_DIV_TOP );
	uRegClkDivTop = ( uRegClkDivTop & ~( 0x7<< 12) )|(poTopBusDiv->uDivAclk133-1 << 12 );
	uRegClkDivTop = ( uRegClkDivTop & ~( 0x7<< 8) )|(poTopBusDiv->uDivAclk160-1 << 8 );
	uRegClkDivTop = ( uRegClkDivTop & ~( 0xf<< 4) )|(poTopBusDiv->uDivAclk100-1 << 4 );
	uRegClkDivTop = ( uRegClkDivTop & ~( 0x7<< 0) )|(poTopBusDiv->uDivAclk200-1 << 0 );

	Outp32( rCLK_DIV_TOP, uRegClkDivTop);
	Outp32( rCLK_DIV_LEFTBUS, ((poTopBusDiv->uDivGpl-1) << 4)|(poTopBusDiv->uDivGdl-1) );
	Outp32( rCLK_DIV_RIGHTBUS, ((poTopBusDiv->uDivGpr-1) << 4)|(poTopBusDiv->uDivGdr-1) );
#else
	SYSC_SetClkDiv(SYSC_DIV_ACLK_200, poTopBusDiv->uDivAclk200);
	SYSC_SetClkDiv(SYSC_DIV_ACLK_100, poTopBusDiv->uDivAclk100);
	SYSC_SetClkDiv(SYSC_DIV_ACLK_160, poTopBusDiv->uDivAclk160);
	SYSC_SetClkDiv(SYSC_DIV_ACLK_133, poTopBusDiv->uDivAclk133);

	if ( poTopBusDiv->uDivGdl > poTopBusDiv->uDivGpl ) {
		SYSC_SetClkDiv(SYSC_DIV_GDL, poTopBusDiv->uDivGdl);
		SYSC_SetClkDiv(SYSC_DIV_GPL, poTopBusDiv->uDivGpl);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_GPL, poTopBusDiv->uDivGpl);
		SYSC_SetClkDiv(SYSC_DIV_GDL, poTopBusDiv->uDivGdl);
	}

	if ( poTopBusDiv->uDivGdr > poTopBusDiv->uDivGdr ) {
		SYSC_SetClkDiv(SYSC_DIV_GDR, poTopBusDiv->uDivGdr);
		SYSC_SetClkDiv(SYSC_DIV_GPR, poTopBusDiv->uDivGdr);
	}
	else {
		SYSC_SetClkDiv(SYSC_DIV_GPR, poTopBusDiv->uDivGdr);
		SYSC_SetClkDiv(SYSC_DIV_GDR, poTopBusDiv->uDivGdr);
	}
#endif
}

void SYSC_SetDivDefaultVal(oCPU_DIV *poCpuDiv, oCORE_DIV *poCoreDiv, oTOPBUS_DIV *poTopBusDiv)
{
	// CPU Divider
	poCpuDiv->uDivCoreM0 = 4;
	poCpuDiv->uDivCoreM1 = 8;
	poCpuDiv->uDivPeriph = 4;
	poCpuDiv->uDivAtb = 4;
	poCpuDiv->uDivPclkDbg = 2;
	poCpuDiv->uDivHpm = 1;
	poCpuDiv->uDivApll = 1;
	poCpuDiv->uDivCore = 1;
	// CORE Divider
	poCoreDiv->uDivDmc = 2;
	poCoreDiv->uDivCoreD = 2;
	poCoreDiv->uDivCoreP = 2;
	poCoreDiv->uDivAcp = 4;
	poCoreDiv->uDivAcpPclk = 2;
	poCoreDiv->uDivDphy = 2;
	poCoreDiv->uDivDpm = 2;
	poCoreDiv->uDivDvsem = 2;
	poCoreDiv->uDivCopy2 = 4;
	poCoreDiv->uDivCoreTimers = 2;
	// TOP Divider, LEFTBUS Driver, RIGHTBUS Driver
	poTopBusDiv->uDivAclk200 = 4;
	poTopBusDiv->uDivAclk100 = 8;
	poTopBusDiv->uDivAclk160 = 5;
	poTopBusDiv->uDivAclk133 = 6;
	poTopBusDiv->uDivGdl = 4;
	poTopBusDiv->uDivGpl = 2;
	poTopBusDiv->uDivGdr = 4;
	poTopBusDiv->uDivGpr = 2;
}

void SYSC_ChangePllnDiv(SYSC_PLL ePll, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv, u32 uLockTime, oCPU_DIV *poCpuDiv, oCORE_DIV *poCoreDiv, oTOPBUS_DIV *poTopBusDiv)
{
	bool bIsClkUpToDn;
	float fCurFout, fSelFreq;

	SYSC_SetLocktimeVal(ePll, uLockTime);

	fCurFout = SYSC_GetFoutPll(ePll);
	fSelFreq = SYSC_CalcPllFout(ePll, uPdiv, uMdiv, uSdiv, uKdiv);

	bIsClkUpToDn = ( fCurFout >= fSelFreq ? TRUE : FALSE);

	switch(ePll)
	{
		case SYSC_APLL:
			// 1. Change ARMCLK source from APLLOUT to MPLLOUT
			SYSC_SetMuxSrc(SYSC_MUX_CORE, 1);	// MUX_CORE : APLL -> MPLL
			// 2. Check changed clock speed (up or down)
			//     down to up (Div->PLL), up to down (PLL->Div)
			if ( bIsClkUpToDn == TRUE ) {
				SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
				SYSC_EnablePll(ePll);
				}
			SYSC_SetCpuDiv(poCpuDiv);
			if ( bIsClkUpToDn == FALSE ) {
				SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
				SYSC_EnablePll(ePll);
				}
			// 3. Change ARMCLK source from MPLLOUT to APLLOUT
			SYSC_SetMuxSrc(SYSC_MUX_CORE, 0);	// MUX_CORE : MPLL -> APLL
			break;
		case SYSC_MPLL:
			//    Check changed clock speed (up or down)
			//     down to up (Div->PLL), up to down (PLL->Div)
			if ( bIsClkUpToDn == TRUE ) {
				SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
				SYSC_EnablePll(ePll);
				}
			SYSC_SetCoreDiv(poCoreDiv);
			SYSC_SetTopBusDiv(poTopBusDiv);
			if ( bIsClkUpToDn == FALSE ) {
				SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
				SYSC_EnablePll(ePll);
				}
			break;
		case SYSC_EPLL:
			SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
			SYSC_EnablePll(ePll);
			SYSC_SetMuxSrc(SYSC_MUX_EPLL, 1);
			break;
		case SYSC_VPLL:
			SYSC_SetPllByPms(ePll, uPdiv, uMdiv, uSdiv, uKdiv);
			SYSC_EnablePll(ePll);
			SYSC_SetMuxSrc(SYSC_MUX_VPLL, 1);
			break;
		default:
			;
	}
}

void SYSC_InitSysClk(SYSC_INIT eInit)
{
	u32 uApllPdiv, uApllMdiv, uApllSdiv;
	u32 uMpllPdiv, uMpllMdiv, uMpllSdiv;

	oCPU_DIV oCpuDiv;
	oCORE_DIV oCoreDiv;
	oTOPBUS_DIV oTopBusDiv;

	if ( eInit == SYSC_INIT_NOR ) {
		SYSC_SetDivDefaultVal( &oCpuDiv, &oCoreDiv, &oTopBusDiv );
		SYSC_ChangePllnDiv( SYSC_MPLL, 6, 200, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// MPLL 800MHz
#if 0
		SYSC_ChangePllnDiv( SYSC_APLL, 6, 200, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// APLL 800MHz
#else
		SYSC_SetMuxSrc(SYSC_MUX_CORE, 1);
		SYSC_SetLocktimeVal(SYSC_APLL, 300);
		SYSC_SetPllByPms(SYSC_APLL, 6, 250, 1, 0);
		SYSC_EnablePll(SYSC_APLL);
#endif
	}
	else if  ( eInit == SYSC_INIT_HIGH ) {
		SYSC_SetDivDefaultVal( &oCpuDiv, &oCoreDiv, &oTopBusDiv );
		SYSC_ChangePllnDiv( SYSC_MPLL, 6, 200, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// MPLL 800MHz
		SYSC_ChangePllnDiv( SYSC_APLL, 6, 250, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// APLL 1000MHz
	}
	else if  ( eInit == SYSC_INIT_LOW ) {
		SYSC_SetDivDefaultVal( &oCpuDiv, &oCoreDiv, &oTopBusDiv );
		SYSC_ChangePllnDiv( SYSC_MPLL, 4, 110, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// MPLL 660MHz
		SYSC_ChangePllnDiv( SYSC_APLL, 6, 200, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// APLL 800MHz
	}
	else if  ( eInit == SYSC_INIT_VERYLOW ) {
		SYSC_SetDivDefaultVal( &oCpuDiv, &oCoreDiv, &oTopBusDiv );
		SYSC_ChangePllnDiv( SYSC_MPLL, 6, 200, 1, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// MPLL 800MHz
		SYSC_ChangePllnDiv( SYSC_APLL, 6, 200, 4, 0, 300, &oCpuDiv, &oCoreDiv, &oTopBusDiv );	// APLL 100MHz
	}
	else
		;

	return;
}

void SYSC_SetPllByFout(SYSC_PLL ePLL, u32 uFout)
{
	u32 uMdiv=0, uPdiv=0, uSdiv=0, uKdiv=0;

	if (ePLL==SYSC_APLL)
	{
		switch(uFout)
		{
			case 1000*1000000: 
				uMdiv = 250; uPdiv = 6; uSdiv = 1; break;
			case 800*1000000: 
				uMdiv = 200; uPdiv = 6; uSdiv = 1; break;
			default: ;
		}
	}
	else if (ePLL==SYSC_MPLL)
	{
		switch(uFout)
		{
			case 800*1000000: 
				uMdiv = 200; uPdiv = 6; uSdiv = 1; break;
			default: ;
		}
	}
	else if (ePLL==SYSC_EPLL)
	{
		switch(uFout)
		{
			case 48*1000000: 
				uMdiv = 48; uPdiv = 3; uSdiv = 3; uKdiv = 0; break;
			case 96*1000000: 
				uMdiv = 48; uPdiv = 3; uSdiv = 2; uKdiv = 0; break;
			case 144*1000000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 2; uKdiv = 0; break;
			case 192*1000000: 
				uMdiv = 48; uPdiv = 3; uSdiv = 1; uKdiv = 0; break;
			case 288*1000000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 1; uKdiv = 0; break;
			case 84*1000000: 
				uMdiv = 42; uPdiv = 3; uSdiv = 2; uKdiv = 0; break;
			case 50*1000000: 
				uMdiv = 50; uPdiv = 3; uSdiv = 3; uKdiv = 0; break;
			case 80*1000000: 
				uMdiv = 80; uPdiv = 3; uSdiv = 3; uKdiv = 0; break;
			case 32768*1000: 
				uMdiv = 65; uPdiv = 3; uSdiv = 4; uKdiv = 35127; break;
			case 49152*1000: 
				uMdiv = 49; uPdiv = 3; uSdiv = 3; uKdiv = 9961; break;
			case 677376*100: 
				uMdiv = 67; uPdiv = 3; uSdiv = 3; uKdiv = 48339; break;
			case 73728*1000: 
				uMdiv = 73; uPdiv = 3; uSdiv = 3; uKdiv = 47710; break;
			case 451584*100: 
				uMdiv = 45; uPdiv = 3; uSdiv = 3; uKdiv = 10381; break;
			default: ;
		}
	}
	else if (ePLL==SYSC_VPLL)
	{
		switch(uFout)
		{
			case 54*1000000: 
				uMdiv = 53; uPdiv = 3; uSdiv = 3; uKdiv = 1024; break;
			case 108*1000000: 
				uMdiv = 53; uPdiv = 3; uSdiv = 2; uKdiv = 1024; break;
			case 74250*1000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 3; uKdiv = 2304; break;
			case 148500*1000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 2; uKdiv = 2304; break;
			case 222750*1000: 
				uMdiv = 36; uPdiv = 2; uSdiv = 1; uKdiv = 1152; break;
			case 371250*1000: 
				uMdiv = 44; uPdiv = 3; uSdiv = 0; uKdiv = 2464; break;
			case 445500*1000: 
				uMdiv = 36; uPdiv = 2; uSdiv = 0; uKdiv = 1152; break;
			case 74176*1000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 3; uKdiv = 2228; break;
			case 148352*1000: 
				uMdiv = 72; uPdiv = 3; uSdiv = 2; uKdiv = 2228; break;
			case 222527*1000: 
				uMdiv = 36; uPdiv = 2; uSdiv = 1; uKdiv = 1114; break;
			case 370883*1000: 
				uMdiv = 44; uPdiv = 3; uSdiv = 0; uKdiv = 2417; break;
			case 445055*1000: 
				uMdiv = 36; uPdiv = 2; uSdiv = 0; uKdiv = 1114; break;
			case 519234*1000: 
				uMdiv = 63; uPdiv = 3; uSdiv = 0; uKdiv = 1950; break;
			case 20027*1000: 
				uMdiv = 53; uPdiv = 3; uSdiv = 4; uKdiv = 1079; break;
			case 27000*1000: 
				uMdiv = 53; uPdiv = 3; uSdiv = 4; uKdiv = 1024; break;
			case 600*1000000: 
				uMdiv = 49; uPdiv = 2; uSdiv = 0; uKdiv = 1024; break;
			case 300*1000000: 
				uMdiv = 49; uPdiv = 2; uSdiv = 1; uKdiv = 1024; break;
			default: ;
		}
	}

	SYSC_SetPllByPms(ePLL, uPdiv, uMdiv, uSdiv, uKdiv);
}

float SYSC_SetPllByPms(SYSC_PLL ePLL, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	float fPllFout;

	switch(ePLL) {
		case SYSC_APLL :
			fPllFout = SYSC_SetPll4508(rAPLL_CON0, uPdiv, uMdiv, uSdiv);
			break;

		case SYSC_MPLL :
			fPllFout = SYSC_SetPll4508(rMPLL_CON0, uPdiv, uMdiv, uSdiv);
			break;

		case SYSC_EPLL :
			fPllFout = SYSC_SetPll4600(rEPLL_CON0, uPdiv, uMdiv, uSdiv, uKdiv);
			break;

		case SYSC_VPLL :
			fPllFout = SYSC_SetPll4650(rVPLL_CON0, uPdiv, uMdiv, uSdiv, uKdiv);
			break;
		default : ;
	}

	return fPllFout;
}

float SYSC_GetVcoPll(SYSC_PLL ePLL)
{
	float fFvco;

	switch(ePLL) {

		case SYSC_APLL :
			fFvco = SYSC_GetVcoPll4508(rAPLL_CON0);
			break;

		case SYSC_MPLL :
			fFvco = SYSC_GetVcoPll4508(rMPLL_CON0);
			break;

		case SYSC_EPLL :
			fFvco = SYSC_GetVcoPll4600(rEPLL_CON0);
			break;

		case SYSC_VPLL :
			fFvco = SYSC_GetVcoPll4650(rVPLL_CON0);
			break;

		default : ;
	}

	return fFvco;
}

float SYSC_GetFoutPll(SYSC_PLL ePLL)
{
	float fPllFout;

	switch(ePLL) {

		case SYSC_APLL :
			fPllFout = SYSC_GetFoutPll4508(rAPLL_CON0);
			break;

		case SYSC_MPLL :
			fPllFout = SYSC_GetFoutPll4508(rMPLL_CON0);
			break;

		case SYSC_EPLL :
			fPllFout = SYSC_GetFoutPll4600(rEPLL_CON0);
			break;

		case SYSC_VPLL :
			fPllFout = SYSC_GetFoutPll4650(rVPLL_CON0);
			break;

		default : ;
	}

	return fPllFout;
}

float SYSC_CalcPllFout(SYSC_PLL ePLL, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	float fPllFout;

	switch(ePLL) {

		case SYSC_APLL :
			fPllFout = SYSC_CalcPll4508(uPdiv, uMdiv, uSdiv);
			break;

		case SYSC_MPLL :
			fPllFout = SYSC_CalcPll4508(uPdiv, uMdiv, uSdiv);
			break;

		case SYSC_EPLL :
			fPllFout = SYSC_CalcPll4600(uPdiv, uMdiv, uSdiv, uKdiv);
			break;

		case SYSC_VPLL :
			fPllFout = SYSC_CalcPll4650(uPdiv, uMdiv, uSdiv, uKdiv);
			break;

		default : ;
	}

	return fPllFout;
}

void SYSC_SetLocktimeVal(SYSC_PLL ePLL, u32 uMicroSec)
{
	u32 uLockCount;
	u32 uRegAddr;

	uLockCount = (u32)((float)uMicroSec/((float)(1.0e6/(float)FIN)));

	switch(ePLL)
	{
		case SYSC_APLL : uRegAddr = rAPLL_LOCK; break;
		case SYSC_MPLL : uRegAddr = rMPLL_LOCK; break;
		case SYSC_EPLL : uRegAddr = rEPLL_LOCK; break;
		case SYSC_VPLL : uRegAddr = rVPLL_LOCK; break;
		default : ;
	}

	SetBits(uRegAddr, 0, 0xffff, uLockCount);
}

u32 SYSC_CheckPllLock(SYSC_PLL ePLL)
{
	u32 uRegAddr;

	switch(ePLL)
	{
		case SYSC_APLL : uRegAddr = rAPLL_CON0; break;
		case SYSC_MPLL : uRegAddr = rMPLL_CON0; break;
		case SYSC_EPLL : uRegAddr = rEPLL_CON0; break;
		case SYSC_VPLL : uRegAddr = rVPLL_CON0; break;
		default : ;
	}

	return GetBits(uRegAddr, 29, 1);
}

void SYSC_EnablePll(SYSC_PLL ePLL)
{
	u32 uRegAddr;

	switch(ePLL)
	{
		case SYSC_APLL : uRegAddr = rAPLL_CON0; break;
		case SYSC_MPLL : uRegAddr = rMPLL_CON0; break;
		case SYSC_EPLL : uRegAddr = rEPLL_CON0; break;
		case SYSC_VPLL : uRegAddr = rVPLL_CON0; break;
		default : ;
	}

	SetBits(uRegAddr, 31, 0x1, 1);			// Enable PLL
	while( GetBits(uRegAddr, 29, 1)==0 );	// Wait until locking pll
}

void SYSC_DisablePll(SYSC_PLL ePLL)
{
	u32 uRegAddr;

	switch(ePLL)
	{
		case SYSC_APLL : uRegAddr = rAPLL_CON0; break;
		case SYSC_MPLL : uRegAddr = rMPLL_CON0; break;
		case SYSC_EPLL : uRegAddr = rEPLL_CON0; break;
		case SYSC_VPLL : uRegAddr = rVPLL_CON0; break;
		default : ;
	}

	SetBits(uRegAddr, 31, 0x1, 0);
}

void SYSC_SetDitherParam( bool bEnDither, u32 uMrr, u32 uMfr, SYSC_DITHER eDitherMethod)
{
	SetBits( rVPLL_CON1, 29, 0x3, (u32)eDitherMethod );
	SetBits( rVPLL_CON1, 24, 0x1f, uMrr );
	SetBits( rVPLL_CON1, 16, 0x3f, uMfr );
	SetBits( rVPLL_CON1, 31, 0x1, (u32)bEnDither );
}

// History
// 2010.04.06 : change AFC value setting code
//                    MSC guided to use AFC_ENB=1 always
static float SYSC_SetPll4508(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv)
{
	u32 uFsel=1;		//	0: FVCO_OUT = FREF 1: FVCO_OUT = FVCO

	float fFvco;
	float fPllFout;

	u32 uPllCon0_addr;
	u32 uPllCon1_addr;

	uPllCon0_addr = uConBaseAddr;
	uPllCon1_addr = uConBaseAddr+4;

	// Check the Fvco Range & Check AFC
	fFvco = (2*(FIN/uPdiv)*uMdiv)/1000000;

	if ( (fFvco>=1500)&&(fFvco<=2100) )
		Outp32( uPllCon1_addr, (0<<31)|(28) );		// AFC value
	else if ( (fFvco>=1100)&&(fFvco<=2500) )
		Outp32( uPllCon1_addr, (0<<31)|(13) );		// AFC value
	else
		Outp32( uPllCon1_addr, (0<<31)|(5) );		// AFC value

	if( GetBits(uPllCon0_addr, 31, 1)==1 )	// Pll is running
		Outp32( uPllCon0_addr, (1<<31)|(0<<28)|(uFsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );
	else		// Pll is stopped
		Outp32( uPllCon0_addr, (0<<31)|(0<<28)|(uFsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );

	fPllFout = ((float)(FIN>>(uSdiv-1))/(float)uPdiv)*(float)uMdiv;

	return fPllFout;
}

static float SYSC_SetPll4600(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	u32 uVsel=1;

	float fFvco;
	float fPllFout;

	u32 uPllCon0_addr;
	u32 uPllCon1_addr;

	uPllCon0_addr = uConBaseAddr;
	uPllCon1_addr = uConBaseAddr + 0x4;

	fFvco = (((float)FIN/(float)uPdiv)*((float)uMdiv+(float)uKdiv/65536.))/1000000.;
	if ( (fFvco>=330) && (fFvco<=460) ) 
		uVsel = 0;
	else if ( (fFvco>460) && (fFvco<=660) )
		uVsel = 1;
	else 
		;

	Outp32( uPllCon1_addr, uKdiv );

	if( GetBits(uPllCon0_addr, 31, 1)==1 )	// Pll is running
		Outp32( uPllCon0_addr, (1<<31)|(uVsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );
	else		// Pll is stopped
		Outp32( uPllCon0_addr, (0<<31)|(uVsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/65536.);

	return fPllFout;
}

static float SYSC_SetPll4650(u32 uConBaseAddr, u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	u32 uVsel=1;

	float fFvco;
	float fPllFout;

	u32 uPllCon0_addr;
	u32 uPllCon1_addr;

	uPllCon0_addr = uConBaseAddr;
	uPllCon1_addr = uConBaseAddr + 0x4;

	fFvco = (((float)FIN/(float)uPdiv)*((float)uMdiv+(float)uKdiv/1024.))/1000000.;
	if ( (fFvco>=330) && (fFvco<=460) ) 
		uVsel = 0;
	else if ( (fFvco>460) && (fFvco<=660) )
		uVsel = 1;
	else 
		;

	SetBits(uPllCon1_addr,0,0xfff,uKdiv);	// K divider

	if( GetBits(uPllCon0_addr, 31, 1)==1 )	// Pll is running
		Outp32( uPllCon0_addr, (1<<31)|(uVsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );
	else		// Pll is stopped
		Outp32( uPllCon0_addr, (0<<31)|(uVsel<<27)|(uMdiv<<16)|(uPdiv<<8)|(uSdiv) );

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/1024.);

	return fPllFout;
}

static float SYSC_GetVcoPll4508(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv;
	float fFvco;

	uMdiv = GetBits(uConBaseAddr, 16, 0x3ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);

	fFvco = (2*(FIN/uPdiv)*uMdiv)/1000000;

	return fFvco;
}

static float SYSC_GetVcoPll4600(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv, uKdiv;
	float fFvco;

	uMdiv = GetBits(uConBaseAddr, 16, 0x1ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);
	uKdiv = GetBits(uConBaseAddr+0x4, 0, 0xffff);

	fFvco = (((float)FIN/(float)uPdiv)*((float)uMdiv+(float)uKdiv/65536.))/1000000.;
	
	return fFvco;
}

static float SYSC_GetVcoPll4650(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv, uKdiv;
	float fFvco;

	uMdiv = GetBits(uConBaseAddr, 16, 0x1ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);
	uKdiv = GetBits(uConBaseAddr+0x4, 0, 0xfff);

	fFvco = (((float)FIN/(float)uPdiv)*((float)uMdiv+(float)uKdiv/1024.))/1000000.;
	
	return fFvco;
}

static float SYSC_GetFoutPll4508(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv;
	float fPllFout;

	uMdiv = GetBits(uConBaseAddr, 16, 0x3ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);

	fPllFout = ((float)(FIN>>(uSdiv-1))/(float)uPdiv)*(float)uMdiv;

	return fPllFout;
}

static float SYSC_GetFoutPll4600(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv, uKdiv;
	float fPllFout;

	uMdiv = GetBits(uConBaseAddr, 16, 0x1ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);
	uKdiv = GetBits(uConBaseAddr+0x4, 0, 0xffff);

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/65536.);

	return fPllFout;
}

static float SYSC_GetFoutPll4650(u32 uConBaseAddr)
{
	u32 uPdiv, uMdiv, uSdiv, uKdiv;
	float fPllFout;

	uMdiv = GetBits(uConBaseAddr, 16, 0x1ff);
	uPdiv = GetBits(uConBaseAddr, 8, 0x3f);
	uSdiv = GetBits(uConBaseAddr, 0, 0x7);
	uKdiv = GetBits(uConBaseAddr+0x4, 0, 0xfff);

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/1024.);

	return fPllFout;
}

static float SYSC_CalcPll4508(u32 uPdiv, u32 uMdiv, u32 uSdiv)
{
	float fPllFout;

	fPllFout = ((float)(FIN>>(uSdiv-1))/(float)uPdiv)*(float)uMdiv;

	return fPllFout;
}

static float SYSC_CalcPll4600(u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	float fPllFout;

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/65536.);

	return fPllFout;
}

static float SYSC_CalcPll4650(u32 uPdiv, u32 uMdiv, u32 uSdiv, u32 uKdiv)
{
	float fPllFout;

	fPllFout = ((float)(FIN>>uSdiv)/(float)uPdiv)*((float)uMdiv+(float)uKdiv/1024.);

	return fPllFout;
}

void SYSC_SetMuxSrc(SYSC_MUX eMux, u32 uMuxSelVal)
{
	u32 uMaxMuxSelVal;

//	uMaxMuxSelVal = (1<<aoMuxSel[eMux].uMaskBit) - 1;
	uMaxMuxSelVal = aoMuxSel[eMux].uMaskBit + 1;

	if(uMuxSelVal>uMaxMuxSelVal) NULL;// do nothing
	
	switch(aoMuxSel[eMux].bIsDmux)
	{
		case SYSC_DMUX :
			SYSC_SetDeglitchMux(eMux, uMuxSelVal);
			break;
		case SYSC_NMUX :
			SYSC_SetNormalMux(eMux, uMuxSelVal);
			break;
		default :
			;
	}
}

u32 SYSC_GetMuxSrc(SYSC_MUX eMux)
{
	u32 uMuxSelVal;

	uMuxSelVal = GetBits(aoMuxSel[eMux].uSetAddr, aoMuxSel[eMux].uOffset, aoMuxSel[eMux].uMaskBit);

	return uMuxSelVal;
}

static void SYSC_SetDeglitchMux(SYSC_MUX eMux, u32 uMuxSelVal)
{
	u32 uStat;
	
	SetBits(aoMuxSel[eMux].uSetAddr, aoMuxSel[eMux].uOffset, aoMuxSel[eMux].uMaskBit, uMuxSelVal);

	do
	{
		uStat = (Inp32(aoMuxSel[eMux].uMonAddr) >> aoMuxSel[eMux].uOffset) & 0x7;
	} while( (uStat==0)||(uStat>2) );
}

static void SYSC_SetNormalMux(SYSC_MUX eMux, u32 uMuxSelVal)
{
	SetBits(aoMuxSel[eMux].uMonAddr, aoMuxSel[eMux].uOffset, 0x1, 0);	// Mask output of Mux
	SetBits(aoMuxSel[eMux].uSetAddr, aoMuxSel[eMux].uOffset, aoMuxSel[eMux].uMaskBit, uMuxSelVal);
	SetBits(aoMuxSel[eMux].uMonAddr, aoMuxSel[eMux].uOffset, 0x1, 1);	// Unmask output of Mux
}

void SYSC_SetClkDiv(SYSC_DIV eDiv, u32 uRatio)
{
	u32 uStat;
	u32 uMaxRatioVal;

//	uMaxRatioVal = 1<<aoDivRatio[eDiv].uMaskBit;
	uMaxRatioVal = 1+aoDivRatio[eDiv].uMaskBit;

	if(uRatio>uMaxRatioVal) NULL;// do nothing

	SetBits(aoDivRatio[eDiv].uSetAddr, aoDivRatio[eDiv].uOffset, aoDivRatio[eDiv].uMaskBit, uRatio-1);

	do{
		uStat = (Inp32(aoDivRatio[eDiv].uMonAddr) >> aoDivRatio[eDiv].uOffset)&0x1;
	} while(uStat);
}

u32 SYSC_GetClkDiv(SYSC_DIV eDiv)
{
	u32 uRatio;

	uRatio = GetBits(aoDivRatio[eDiv].uSetAddr, aoDivRatio[eDiv].uOffset, aoDivRatio[eDiv].uMaskBit);

	return uRatio+1;
}

void SYSC_SetClkGateIp(SYSC_GATE_IP eIp, bool bIsPass)
{
	if(bIsPass>1) NULL;// do nothing
	SetBits(aoGateIp[eIp].uSetAddr, aoGateIp[eIp].uOffset, aoGateIp[eIp].uMaskBit, bIsPass);
}

u32 SYSC_GetClkGateIp(SYSC_GATE_IP eIp)
{
	bool bIsPass;

	bIsPass = GetBits(aoGateIp[eIp].uSetAddr, aoGateIp[eIp].uOffset, aoGateIp[eIp].uMaskBit);

	return bIsPass;
}

void SYSC_SetClkGateBlock(SYSC_GATE_BLK eBlk, bool bIsPass)
{
	if(bIsPass>1) NULL;// do nothing
	SetBits(aoGateBlk[eBlk].uSetAddr, aoGateBlk[eBlk].uOffset, aoGateBlk[eBlk].uMaskBit, bIsPass);
}

u32 SYSC_GetClkGateBlock(SYSC_GATE_BLK eBlk)
{
	bool bIsPass;

	bIsPass = GetBits(aoGateBlk[eBlk].uSetAddr, aoGateBlk[eBlk].uOffset, aoGateBlk[eBlk].uMaskBit);

	return bIsPass;
}

static float SYSC_GetMuxClkOut(SYSC_MUX eMux)
{
	u32 uMuxSelVal;
	float fMuxClkOut;

	u32 uSclkHdmi27m = 27000000;
	u32 uSclkHdmiPhy = 27000000;
	u32 uSclkUsbPhy0 = 48000000;
	u32 uSclkUsbPhy1 = 48000000;
	u32 uSpdifExtClk = 27000000;
	
	switch(eMux)
	{
		case SYSC_MUX_APLL :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLLFOUT) : FIN;
			break;
		case SYSC_MUX_APLLFOUT :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetVcoPll(SYSC_APLL) : SYSC_GetFoutPll(SYSC_APLL);
			break;
		case SYSC_MUX_MPLL :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_MPLLFOUT) : FIN;
			break;
		case SYSC_MUX_MPLLFOUT :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetVcoPll(SYSC_MPLL) : SYSC_GetFoutPll(SYSC_MPLL);
			break;
		case SYSC_MUX_CORE :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_MPLL) : SYSC_GetMuxClkOut(SYSC_MUX_APLL);
			break;
		case SYSC_MUX_HPM :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_MPLL) : SYSC_GetMuxClkOut(SYSC_MUX_APLL);
			break;
		case SYSC_MUX_CORE_BUS :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_DPHY :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_CORE_TIMERS :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_ACLK_200 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_ACLK_100 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_ACLK_160 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_ACLK_133 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_ONENAND :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_ACLK_160)/SYSC_GetClkDiv(SYSC_DIV_ACLK_160) : SYSC_GetMuxClkOut(SYSC_MUX_ACLK_133)/SYSC_GetClkDiv(SYSC_DIV_ACLK_133);
			break;
		case SYSC_MUX_EPLL :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetFoutPll(SYSC_EPLL) : FIN;
			break;
		case SYSC_MUX_VPLLSRC :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? uSclkHdmi27m : FIN;
			break;
		case SYSC_MUX_VPLL :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetFoutPll(SYSC_VPLL) : SYSC_GetMuxClkOut(SYSC_MUX_VPLLSRC);
			break;
		case SYSC_MUX_GDL :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_GDR :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_DAC :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? uSclkHdmiPhy : SYSC_GetMuxSrc(SYSC_MUX_VPLL);
			break;
		case SYSC_MUX_HDMI :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? uSclkHdmiPhy : SYSC_GetMuxSrc(SYSC_MUX_VPLL)/SYSC_GetClkDiv(SYSC_DIV_TV_BLK); 
			break;
		case SYSC_MUX_MIXER :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_HDMI) : SYSC_GetMuxClkOut(SYSC_MUX_DAC);
			break;
		case SYSC_MUX_SATA :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_MFC_0 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_MFC_1 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_VPLL) : SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			break;
		case SYSC_MUX_MFC :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_MFC_1) : SYSC_GetMuxClkOut(SYSC_MUX_MFC_0);
			break;
		case SYSC_MUX_G3D_0 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_G3D_1 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_VPLL) : SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			break;
		case SYSC_MUX_G3D :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_G3D_1) : SYSC_GetMuxClkOut(SYSC_MUX_G3D_0);
			break;
		case SYSC_MUX_G2D_0 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_APLL)/SYSC_GetClkDiv(SYSC_DIV_APLL) : SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			break;
		case SYSC_MUX_G2D_1 :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_VPLL) : SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			break;
		case SYSC_MUX_G2D :
			fMuxClkOut = SYSC_GetMuxSrc(eMux) ? SYSC_GetMuxClkOut(SYSC_MUX_G2D_1) : SYSC_GetMuxClkOut(SYSC_MUX_G2D_0);
			break;
		case SYSC_MUX_AUDIO0 :
			uMuxSelVal = SYSC_GetMuxSrc(eMux);
			if(uMuxSelVal==0) ;// fMuxClkOut=AUDIOCDCLK0;
			else if(uMuxSelVal==1) ; // Reserved
			else if(uMuxSelVal==2) fMuxClkOut=uSclkHdmi27m;
			else if(uMuxSelVal==3) fMuxClkOut=uSclkUsbPhy0;
			else if(uMuxSelVal==4) fMuxClkOut=uSclkUsbPhy1;
			else if(uMuxSelVal==5) fMuxClkOut=uSclkHdmiPhy;
			else if(uMuxSelVal==6) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			else if(uMuxSelVal==7) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			else if(uMuxSelVal==8) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_VPLL);
			else ;
			break;
		case SYSC_MUX_AUDIO1 :
			uMuxSelVal = SYSC_GetMuxSrc(eMux);
			if(uMuxSelVal==0) ;// fMuxClkOut=AUDIOCDCLK1;
			else if(uMuxSelVal==1) ; // Reserved
			else if(uMuxSelVal==2) fMuxClkOut=uSclkHdmi27m;
			else if(uMuxSelVal==3) fMuxClkOut=uSclkUsbPhy0;
			else if(uMuxSelVal==4) fMuxClkOut=uSclkUsbPhy1;
			else if(uMuxSelVal==5) fMuxClkOut=uSclkHdmiPhy;
			else if(uMuxSelVal==6) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			else if(uMuxSelVal==7) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			else if(uMuxSelVal==8) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_VPLL);
			else ;
			break;
		case SYSC_MUX_AUDIO2 :
			uMuxSelVal = SYSC_GetMuxSrc(eMux);
			if(uMuxSelVal==0) ;// fMuxClkOut=AUDIOCDCLK2;
			else if(uMuxSelVal==1) ; // Reserved
			else if(uMuxSelVal==2) fMuxClkOut=uSclkHdmi27m;
			else if(uMuxSelVal==3) fMuxClkOut=uSclkUsbPhy0;
			else if(uMuxSelVal==4) fMuxClkOut=uSclkUsbPhy1;
			else if(uMuxSelVal==5) fMuxClkOut=uSclkHdmiPhy;
			else if(uMuxSelVal==6) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			else if(uMuxSelVal==7) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			else if(uMuxSelVal==8) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_VPLL);
			else ;
			break;
		case SYSC_MUX_CSIS0 :
		case SYSC_MUX_CSIS1 :
		case SYSC_MUX_CAM0 :
		case SYSC_MUX_CAM1 :
		case SYSC_MUX_FIMC0_LCLK :
		case SYSC_MUX_FIMC1_LCLK :
		case SYSC_MUX_FIMC2_LCLK :
		case SYSC_MUX_FIMC3_LCLK :
		case SYSC_MUX_MMC0 :
		case SYSC_MUX_MMC1 :
		case SYSC_MUX_MMC2 :
		case SYSC_MUX_MMC3 :
		case SYSC_MUX_MMC4 :
		case SYSC_MUX_FIMD0 :
		case SYSC_MUX_FIMD1 :
		case SYSC_MUX_MDNIE0 :
		case SYSC_MUX_MDNIE1 :
		case SYSC_MUX_MDNIE_PWM0 :
		case SYSC_MUX_MDNIE_PWM1 :
		case SYSC_MUX_MIPI0 :
		case SYSC_MUX_MIPI1 :
		case SYSC_MUX_SPI0 :
		case SYSC_MUX_SPI1 :
		case SYSC_MUX_SPI2 :
		case SYSC_MUX_SPI3 :
		case SYSC_MUX_UART0 :
		case SYSC_MUX_UART1 :
		case SYSC_MUX_UART2 :
		case SYSC_MUX_UART3 :
		case SYSC_MUX_UART4 :
		case SYSC_MUX_PWM :
		case SYSC_MUX_PWI :
			uMuxSelVal = SYSC_GetMuxSrc(eMux);
			if(uMuxSelVal==0) fMuxClkOut=FIN;
			else if(uMuxSelVal==1) fMuxClkOut=FIN;
			else if(uMuxSelVal==2) fMuxClkOut=uSclkHdmi27m;
			else if(uMuxSelVal==3) fMuxClkOut=uSclkUsbPhy0;
			else if(uMuxSelVal==4) fMuxClkOut=uSclkUsbPhy1;
			else if(uMuxSelVal==5) fMuxClkOut=uSclkHdmiPhy;
			else if(uMuxSelVal==6) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_MPLL);
			else if(uMuxSelVal==7) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_EPLL);
			else if(uMuxSelVal==8) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_VPLL);
			else ;
			break;
		case SYSC_MUX_SPDIF :
			uMuxSelVal = SYSC_GetMuxSrc(eMux);
			if(uMuxSelVal==0) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_AUDIO0)/SYSC_GetClkDiv(SYSC_DIV_AUDIO0);
			else if(uMuxSelVal==1) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_AUDIO1)/SYSC_GetClkDiv(SYSC_DIV_AUDIO1);
			else if(uMuxSelVal==2) fMuxClkOut=SYSC_GetMuxClkOut(SYSC_MUX_AUDIO2)/SYSC_GetClkDiv(SYSC_DIV_AUDIO2);
			else if(uMuxSelVal==3) fMuxClkOut=uSpdifExtClk;
			else ;
			break;
		default : ;
	}

	return fMuxClkOut;
}

void SYSC_SetClkOut( SYSC_CLKOUT eClkOut, u32 uDivVal )
{
	switch(eClkOut)
	{
		case SYSC_CLKOUT_LEFTBUS_SCLK_MPLL_2 :
		case SYSC_CLKOUT_LEFTBUS_SCLK_APLL_2 :
		case SYSC_CLKOUT_LEFTBUS_ACLK_GDL :
		case SYSC_CLKOUT_LEFTBUS_ACLK_GPL :
			SetBits(0x10020a00, 8, 0xf, 2);
			SYSC_SetCmuClkOut(eClkOut, uDivVal );
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_RIGHTBUS_SCLK_MPLL_2 :
		case SYSC_CLKOUT_RIGHTBUS_SCLK_APLL_2 :
		case SYSC_CLKOUT_RIGHTBUS_ACLK_GDR :
		case SYSC_CLKOUT_RIGHTBUS_ACLK_GPR :
			SetBits(0x10020a00, 8, 0xf, 3);
			SYSC_SetCmuClkOut(eClkOut, uDivVal );
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_TOP_EPLL_FOUT :
		case SYSC_CLKOUT_TOP_VPLL_FOUT :
		case SYSC_CLKOUT_TOP_SCLK_HDMI27M :
		case SYSC_CLKOUT_TOP_SCLK_USBPHY0 :
		case SYSC_CLKOUT_TOP_SCLK_USBPHY1 :
		case SYSC_CLKOUT_TOP_SCLK_HDMIPHY :
		case SYSC_CLKOUT_TOP_AUDIOCDCLK0 :
		case SYSC_CLKOUT_TOP_AUDIOCDCLK1 :
		case SYSC_CLKOUT_TOP_AUDIOCDCLK2 :
		case SYSC_CLKOUT_TOP_SPDIF_EXTCLK :
		case SYSC_CLKOUT_TOP_ACLK_160 :
		case SYSC_CLKOUT_TOP_ACLK_133 :
		case SYSC_CLKOUT_TOP_ACLK_200 :
		case SYSC_CLKOUT_TOP_ACLK_100 :
		case SYSC_CLKOUT_TOP_SCLK_MFC :
		case SYSC_CLKOUT_TOP_SCLK_G3D :
		case SYSC_CLKOUT_TOP_SCLK_G2D :
		case SYSC_CLKOUT_TOP_CAM_A_PCLK :
		case SYSC_CLKOUT_TOP_CAM_B_PCLK :
		case SYSC_CLKOUT_TOP_S_RXBYTECLKHS0_2L :
		case SYSC_CLKOUT_TOP_S_RXBYTECLKHS0_4L :
		case SYSC_CLKOUT_TOP_RX_HALF_BYTE_CLK_CSIS0 :
		case SYSC_CLKOUT_TOP_RX_HALF_BYTE_CLK_CSIS1 :
			SetBits(0x10020a00, 8, 0xf, 1);
			SYSC_SetCmuClkOut(eClkOut, uDivVal );
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_CORE_ACLK_CORED :
		case SYSC_CLKOUT_CORE_ACLK_COREP :
		case SYSC_CLKOUT_CORE_ACLK_ACP :
		case SYSC_CLKOUT_CORE_PCLK_ACP :
		case SYSC_CLKOUT_CORE_SCLK_DMC :
		case SYSC_CLKOUT_CORE_SCLK_DPHY :
		case SYSC_CLKOUT_CORE_SCLK_CORE_TIMERS :
		case SYSC_CLKOUT_CORE_SCLK_PWI :
			SetBits(0x10020a00, 8, 0xf, 0);
			SYSC_SetCmuClkOut(eClkOut, uDivVal );
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_CPU_APLL_FOUT_2 :
		case SYSC_CLKOUT_CPU_APLL_VCOOUT_4 :
		case SYSC_CLKOUT_CPU_MPLL_FOUT_2 :
		case SYSC_CLKOUT_CPU_MPLL_VCOOUT_4 :
		case SYSC_CLKOUT_CPU_ARMCLK_2 :
		case SYSC_CLKOUT_CPU_ACLK_COREM0 :
		case SYSC_CLKOUT_CPU_ACLK_COREM1 :
		case SYSC_CLKOUT_CPU_ACLK_CORES :
		case SYSC_CLKOUT_CPU_ATCLK :
		case SYSC_CLKOUT_CPU_PERIPHCLK :
		case SYSC_CLKOUT_CPU_PCLK_DBG :
		case SYSC_CLKOUT_CPU_SCLK_HPM :
			SetBits(0x10020a00, 8, 0xf, 4);
			SYSC_SetCmuClkOut(eClkOut, uDivVal );
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_XXTI :
		case SYSC_CLKOUT_XUSBXTI :
		case SYSC_CLKOUT_RTC_TICCLK :
		case SYSC_CLKOUT_RTCCLK :
			SetBits(aoClkOut[eClkOut].uSetAddr, 8, 0xf, aoClkOut[eClkOut].uClkOutMuxVal);	// PMU ClkOut set
			SetBits(0x10020a00, 0, 0x1, 0);	// PMU ClkOut Enable
			break;
		case SYSC_CLKOUT_DISABLE :
			SetBits(0x10020a00, 0, 0x1, 1);	// PMU ClkOut Disable
			break;
		default : ;
	}
}

static void SYSC_SetCmuClkOut( SYSC_CLKOUT eClkOut, u32 uDivVal )
{
	u32 uStat;
	
	SetBits(aoClkOut[eClkOut].uSetAddr, 8, 0xf, uDivVal-1);	// CMU CLKOUT div set

	do { uStat = GetBits(aoClkOut[eClkOut].uSetAddr+0x4, 0, 0x1);
	} while(uStat);	// wait while divider is changing

	SetBits(aoClkOut[eClkOut].uSetAddr, 0, 0x1f, aoClkOut[eClkOut].uClkOutMuxVal);	// CMU CLKOUT set
}
